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Pentium D-Only true dual core?

mytiburon

Limp Gawd
Joined
Apr 11, 2005
Messages
155
Taken from Maxim Pc, sorry if this is old,im a noob

It’s hard enough explaining the differences between multitasking, multiprocessing, multithreading, Hyper-Threading, single-core processors, multicore processors, and multiprocessor systems. Now Intel comes along and throws us another curve ball by announcing multicore processors that are actually multichip modules.

Intel recently announced a bunch of multicore processors with typically obscure code-names. Smithfield, officially christened Pentium D, has two Pentium 4-class processor cores on a single die. It’s a true multicore processor. But when Intel moves to the next-generation 65-nanometer chip-fabrication process, the company will introduce a new desktop processor code-named Presler that encloses two die in one chip package. Presler will look like a multicore processor to the operating system, but inside, it will actually have only one core per die. That’s not quite a true multicore processor.

There’s a common term for a processor like Presler: multichip module (MCM). An MCM is simply a chip package containing two or more die. Old-timers might recall that Intel’s Pentium Pro, introduced in 1995, was also an MCM. It enclosed a processor chip and an SRAM chip in a single package. The SRAM was an external L2 cache, because in those days it was too expensive to integrate a large L2 cache on the same die with the processor. But today, it’s obviously not too expensive to integrate two processor cores on a single die. So why is Presler seemingly taking a step backward?

First answer: economy. The 65nm process shrink will dramatically reduce Intel’s manufacturing cost for a single-core chip. MCMs are more expensive to produce, but Intel has made some advances in this technology since the Pentium Pro. Therefore, it will be cheaper for Intel to stuff two Presler-class dies into a single package than to make a dual-core Presler-class die, even with the additional cost of the MCM package.

Second answer: flexibility. By designing Presler with one core per die, Intel can make a lower-priced Celeron version of Presler with only one die per package. This would be even better for Intel, because the company wouldn’t have to disable part of Presler’s L2 cache to make a lower-end processor (as Intel does today with Celeron), and the single-die package would eliminate the extra cost of the MCM.

So Intel’s multicore strategy certainly makes sense. And most people will call Presler a multicore processor without ever knowing the difference.
 
Interesting. Presler sounds like a pretty cool processor. When again is it coming out?
 
It is true that the two cores in the pentium D are on the same peice of silicon. And that does make it a "dual-core" part.

But, you should really realize that the way in which the cores are connected is more important than their placement on silicon.

These MCMs, or multichip modules, that Intel is comming out with will be a better at dual-core work than the current pentum Ds even though the dies live on different peices of silicon. This is because Intel will (they are supposed to anyways) enable the cores of the new dual-core parts to talk with eachother directly.

This is a lot like AMDs current dual-core chips which can also communitate between cores directly. The pentium D has to share the FSB with the other core and the northbridge, and because this bus is external to the CPU it is quite slow unlike a direct core to core link.
 
visaris said:
It is true that the two cores in the pentium D are on the same peice of silicon. And that does make it a "dual-core" part.

But, you should really realize that the way in which the cores are connected is more important than their placement on silicon.

These MCMs, or multichip modules, that Intel is comming out with will be a better at dual-core work than the current pentum Ds even though the dies live on different peices of silicon. This is because Intel will (they are supposed to anyways) enable the cores of the new dual-core parts to talk with eachother directly.

This is a lot like AMDs current dual-core chips which can also communitate between cores directly. The pentium D has to share the FSB with the other core and the northbridge, and because this bus is external to the CPU it is quite slow unlike a direct core to core link
.

/\ ye speaks the truth.
 
Yonah is a dual core chip on one die. It's not just 2 cores glued together like the A64 by HT links or P4 by CPU bus, but 2 cores sharing one L2 cache.

The cool thing about Yonah is that it only has 14 million more transistors than Dothan. At 65nm it's only around half the size of a 90nm Dothan (~44mm^2 vs 84mm^2).
 
pxc said:
Yonah is a dual core chip on one die. It's not just 2 cores glued together like the A64 by HT links or P4 by CPU bus, but 2 cores sharing one L2 cache.

While it is true that sharing a L2 cache is better than having two separate caches, it is not fair to put current AMD dual-core and current Intel dual core in the same category of "just glued together".

The AMD dual-core parts are not connected by an HT link. They are connected at the SRQ (System Request Queue) which runs at full CPU clockspeed. The pentium D's cores are connected by an 800MHz FSB which is not even close to full CPU clockspeed.

This is a picture of AMD's dual-core layout:
11881.gif



Yonah will be a great step for Intel if they do it correctly (I'm sure they will). And the shared L2 cache layout will actually be a little better than AMDs current offerings. Though, I hear that AMD is also moving to a shared cache design in the future. We are in for some interesting times, that's for sure.
 
The crossbar connects to external access (HT and memory). L1/L2 data sharing between the cores is handled the same way as on multiprocessor Opterons: a HT link between the cores. In that sense, it *is* just 2 cores glued together.

The 945/955 chipsets for the Pentium D have the same functionality as the SRQ/crossbar.

It's not really much different, but AMD's method is more efficient. Intel could really use CSI Interconnect on the desktop now. :(
 
pxc said:
L1/L2 data sharing between the cores is handled the same way as on multiprocessor Opterons: a HT link between the cores. In that sense, it *is* just 2 cores glued together.

I know I really shouldn't make a big deal about this, but that is simply untrue. The two cores in an AMD dual-core chip are not connected by an HT link. They are connected by the SRQ. Core0 can read data out of core1's cache without ever touching the crossbar or the HT links. The two cores in AMD's dual core parts are connected by the SRQ (System Request Queue).

Here is another picture to help out with this:
xbar.jpg


Now, while AMD might currently be in the lead here with their SRQ, I think Intel will take over with their shared cache design when it comes out, though, again, AMD has similar shared cache plans.
 
visaris said:
Now, while AMD might currently be in the lead here with their SRQ, I think Intel will take over with their shared cache design when it comes out, though, again, AMD has similar shared cache plans.

It will take a while for AMD to switch to that shared cache architecture. The K8 had everything except the 2nd core to be a dual core chip so they have not really needed to change much in the past year or two other than simple die shrinks and added SSE3.

I think AMD will only go the shared cache route with their next significant architecture change package.
 
Yonah is going to be great. I just cant wait until Intel figures out that an on die memory controller is a good idea...

Didnt AMD say that It will keep its L1 and L2 caches seperate? But they will introduce a L3 Cache to all their processors that will be shared? I remember that....

Google searching now
 
USMC2Hard4U said:
Yonah is going to be great. I just cant wait until Intel figures out that an on die memory controller is a good idea...

Didnt AMD say that It will keep its L1 and L2 caches seperate? But they will introduce a L3 Cache to all their processors that will be shared? I remember that....

Google searching now

That would be pretty cool actually. I could see it being a bar shaped block of maybe 512kb or 384kb that nestles right in with the SRI. I'd like to see some speculation, sweet sweet speculation! :D
 
Found it! Trusty Anandtech :) From IDF interview with some guy from AMD.

"More than once during our conversations with Weber, it became clear that future multi-core AMD processors will continue to have their L1 and L2 caches separate, but a shared L3 cache will eventually be introduced to help reduce memory latency and keep those cores fed."




http://www.anandtech.com/printarticle.aspx?i=2387
 
Sounds good. With 65nm it shouldnt be an issue yields-wise, and I think killing latency more and more will certainly make up for the lack of clockspeed increases during the past, oh, year.
 
USMC2Hard4U said:
I just cant wait until Intel figures out that an on die memory controller is a good idea...
:p They have. Too bad no Intel processors with on-die memory controllers will be out before 2007. And even then it's not going to be for desktop chips initially.
 
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