Parallel faster than Serial in theory....

R

Rtstrider

Gawd
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Dec 3, 2004
Messages
597
Ok isn't parallel transmission faster than serial? If I understand it best this is how parallel works:

10101010
01010101

and so on, it can transfer more instructions per clock cycle...Now as far as Serial here's how I best understand it:

1000
0100
0010
0001
0000

In this diagram it can only move 1 bit per clock cycle while parallel could move up to 8 bits (my bit's may be off) but this is how I best understand it, and as response to the fs/ft forum (it's the outpost thread with the 300gb seagate for $89 shipped(I will edit this later and put a link right here)) usb is serial transmission as I best understand...So yes the cable is smaller, but cannot transfer as many bits as parallel can, or at least in theory that's how it should work. So my question is...Why are Sata hd's just as faster or maybe a tad faster than the pata hd's?
 
I believe interferance is the reason but I really have no firm idea.
 
Ah someone did go and start a thread, this would be better suited for the Hard Drive section btw.
 
They don't have the same clock.

PATA signals interfere with each other. That's why ATA66 and faster have the extra ground wires. By serialising the data stream, the interface clock can be sped up - a lot.
 
Are you talking about hard drive interfaces or serial/parallel communication in general?

Firstly, you can transmit more than 8 bits in parallel. Just think about the address and data busses in your computer. A lot of systems can do 64 bits in parallel. Sending the same number of bits in the same amount of time would require a significantly faster clock; faster than anything we can do today. However, things begin to break down when you have a high transmission speed and a significant transmission distance.

In addition the the interference issues mentioned, there's the problem of ensuring that each bit in a parallel stream arrives at the exact same time. It seems like they would no matter what, but at very high speeds, even the smallest differences will slow down transfer speeds. The receiver will have to wait slightly longer before processing the received data to ensure that it has the correct data. This is one of the reasons why motherboard traces sometimes seem to take funky paths. It's to minimize crosstalk and interference and to ensure correct timing of signal propagation.

ps. in your example, if each line is one clock cycle, then you are sending four bits per cycle, which is not a serial transmission.
 
So I knew about the interference, and the extra ground wires in the 80 pin IDE cables...Can someone draw out a better diagram of serial and parallel transimission?
 
And here I was thinking he was talking about good ol' Parallel (1284) and Serial ports.

On that note, I'm kind of pissed that serial ports are dying out. Lots of stuff still requires serial ports for config/transfer. Old TI data cables, and some older Catalysts have that weird 4-pin RJ45 to Serial cable.

@OP: SATA and PATA.
 
Rtstrider said:
So I knew about the interference, and the extra ground wires in the 80 pin IDE cables...Can someone draw out a better diagram of serial and parallel transimission?
Click to expand...
Parallel:
01101010
11011010
10100000
11101101

Serial:
0
1
1
0
1
0
1
0

Each line is a clock cycle.
 
Except with serial the clock is much higher (IDE=133MB/s SATA=300MB/s) so you get an enormous boost in throughput and since each device has its own channel they can communicate simultaneously instead of one at a time.

Plus, SATA drives support NCQ which increases the efficiency of the data seeks and in turn speeds up the sustainable transmission rate.

If you want a better example of ass kickery, check out the newest shizzle, Serial Attached SCSI. We've started using these at work and have been extremely impressed with their performance and expected lifetime. SATA drives (according to the vendor) last about 15000 hours where SAS drives can be expected to last about 40000 hours.

Here, this site breaks down some of the main differences in architecture between all the available interfaces.
http://www.lecroy.com/tm/Solutions/Protocol/sas.asp?menuid=29
 
A good illustration on how hard it gets to route large parallel buses just from a space and complexity standpoint: http://www.simmtester.com/page/news/showpubnews.asp?num=113
About 2/3rd the way down the page, routing to 4 DDR2 DIMMS vs 4 FBDIMMS.

You'd see similar things in PCI (or AGP) vs PCI-Express and IDE vs SATA.

Fewer data lines and easier routing means it's less expensive to do things like diferentail pairs that reduce problems from interferance and make it faster to determine the value of a bit on the data line. Consequently very high clock speeds are possible.
 
But even on a bus that transfer serially can have interference problems at hgh speeds. So a new scheme has to be implemented to cancel out the noise. Thus you have differential signaling. the same signal is sent along two separate lines, but at opposite voltages. eg. -5v and +5v. If the receiver detects a +5v on one line, it'll check the other line for the opposite voltage. If it isn't there then it knows that the signal is noise. Also the signal pairs must be run together so that noise will affect both lines the same way (eg. introduce +5v on both lines). I think that makes since.

Parallel lines howerver will introduce crosstalk at high speeds. even if they're separated by grounds everntually the grounds will propigate the crosstalk instead of blocking it at high enough speeds. You could say that you could implement differential signaling on each parallell interface, (which is SORT of how PCIe does it) but that can become cost prohibitive very quickly. Dual Channel DDR would require 256 data lines, and 64 or 128 addresses lines )32bit or 64bit addresses). that would be up to 384 traces to each DIMM slot on the main board not count the signaling, voltage, and grounding wires. So we'd be buying 500pin SP-DIMMs (stacked pin-dual inline memory module) to keep the sockets small enough to fit on a main board. And after all that work, the clock speeds will still be limited by arrival time of the signals, and crosstalk between signal pairs.

Hope that explains it a bit better. If not, I'm sorry I only think I know what I'm talking about.

Ryan

EDIT: actually differential signaling isn't a new idea, it's been used on the telephone system for at least half a century
 
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