Hi,
I recently bought a 3.0C p4 that had a broken pin. The guy had good references, and says he has fixed it with a wire in the socket. He only mentioned instability, but never mentioned anything about the L2 cache being busted.. Some cache tests completely fail to recognize it, and in Sandra, the cache & memory test there is only testing memory bandwidth, and not cache, as it almost flatlines on the graph. 8kb L1 data cache does show up and seems to work.
When running the CPU math tests in Sandra, while the FPU is on par, the ALU Dhrystone tests are incredibly low. The P4 running at 2ghz scores about 750 ALU, while a stock P4 @ 2ghz should score about 5350. Changing the memory bandwidth changes this number too. Increasing it to 400MHz increases the score to about 1100, as it is not using cache in this test either. To load up explorer windows, it can take me 20 sec to do because of this. I asked the guy about it, and he says he can't remembewr any performance issues of this type.
Now, about the pin, when looking at the pin side, with the corner with the 2 pins not there facing at the top right, the actual broke pin is on the very bottom row, 2nd one from the left. Does anybody have ANY idea what this pin does? I don't have alot of money, and thought I'd purchase it for a good deal, but I feel that the guy was not very honest about it.
Any help that you can provide would be very helpful, especialy the function of this pin, whether or not it'd cause the L2 cache to not work. I'm going to have to spend a little money to have it professionally fixed, and want to verify the function of this pin before I drop anymore money into the chip
Please help if you can.this sucks..
I recently bought a 3.0C p4 that had a broken pin. The guy had good references, and says he has fixed it with a wire in the socket. He only mentioned instability, but never mentioned anything about the L2 cache being busted.. Some cache tests completely fail to recognize it, and in Sandra, the cache & memory test there is only testing memory bandwidth, and not cache, as it almost flatlines on the graph. 8kb L1 data cache does show up and seems to work.
When running the CPU math tests in Sandra, while the FPU is on par, the ALU Dhrystone tests are incredibly low. The P4 running at 2ghz scores about 750 ALU, while a stock P4 @ 2ghz should score about 5350. Changing the memory bandwidth changes this number too. Increasing it to 400MHz increases the score to about 1100, as it is not using cache in this test either. To load up explorer windows, it can take me 20 sec to do because of this. I asked the guy about it, and he says he can't remembewr any performance issues of this type.
Now, about the pin, when looking at the pin side, with the corner with the 2 pins not there facing at the top right, the actual broke pin is on the very bottom row, 2nd one from the left. Does anybody have ANY idea what this pin does? I don't have alot of money, and thought I'd purchase it for a good deal, but I feel that the guy was not very honest about it.
Any help that you can provide would be very helpful, especialy the function of this pin, whether or not it'd cause the L2 cache to not work. I'm going to have to spend a little money to have it professionally fixed, and want to verify the function of this pin before I drop anymore money into the chip
Please help if you can.this sucks..