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Open Source Cache Coherence Protocol Implementation

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Limp Gawd
Joined
Feb 25, 2005
Messages
139
Does anyone know of an open source cache coherence protocol implementation? Preferably written in Verilog? I heard that writing one of these is incredibly hard so I was hoping someone already made one.

I looked on google and opencores but didnt see anything...
 
i know this isn't the reply you want, but i've never heard of such a thing. i'm surprised it exists. i am NOT by ANY means a computer engineer, but i would expect these algorithms to be HIGHLY architecturally dependent. is it commonplace to find open-source, already-implemented hardware algorithms?

edit: i meant to say highly architecturally DEpendent not INDEpendent.
 
I'd agree with Nameless, generally. I guess some open IP implementations for ARM might be a place to start, but an open implementation of this kind of building block seems like a lot to ask. Cache coherency is a key feature towards the performance and scalability of any multi-processor system, and something that's well-guarded IP since it's a direct competitive advantage.
 
additionally, the way the OP asks the question doesn't make any real sense. if i can give you 37 different open-source protocols like the one asked for, do any of them do you any good if they aren't available for your architecture? that's kind of like looking at someone else's 500k-line BeOS application and porting it to Windows Vista, except much worse.

I think the best you're going to be able to do is examine well-known algorithms (really old example: snoopy-bus) and implement them yourself. open algorithms should not be terribly difficult to find... you can find them in any textbook and you can find new ones in new research papers... but i think it will be near impossible to find open-source implementations.

hardware isn't like software... there are millions of people who can download code and reuse it in their own application, but what good would it do you if i gave you a hardware implementation and it's for an architecture that I created which is different than the one you are using?

on a side note, has there been much research in industry or academia on portable hardware development? or are these just what we refer to as 'committee standards' ?
 
It's one of those situations where I can change my architecture to match the protocol. I havent implemented one of these before so I don't really know all of the details (and the details are where it's painful).

I was hoping that there was an academic one available. If there is... it seems to be impossible to find.

That said... what's with the SoC community? Don't they have something or do they just assume that there's a single processor?
 
All of the SoC systems I know about are single proc, single core. The only multi-core embedded part I'm aware of is the Propeller, and that just does a shared round-robin with no caching. It's also in-order execution, so that's simple, too.
 
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