OC - Quantitative Study?

[mysticbyiq]

Has anyone here written or come across a quantitative assessment of OC, with respect to various hardware and instruction sets?

Instruction sets: For instance in my case, the QX6700, when frequency increases as overclocked, loses the Virtual Machine support instructions first (unreliable at 3.2 GHz), then the floating point status register (gone at 3.5 GHz), then the SSE floating point registers (gone at 3.7 GHz), then finally, integer instructions and registers.

Due to internal signal delays, the instructions should stop working in approximately the same order, regardless of the OC cooling and other factors.

 

[MrGuvernment]

how do you test for each of those items to see what has failed?

 

[Arcygenical]

I guess you could write a program that stresses only the individual instructions...

Looping MMX calls for hours to see if it passes.

 

[mwarps]

Has anyone here written or come across a quantitative assessment of OC, with respect to various hardware and instruction sets?

Instruction sets: For instance in my case, the QX6700, when frequency increases as overclocked, loses the Virtual Machine support instructions first (unreliable at 3.2 GHz), then the floating point status register (gone at 3.5 GHz), then the SSE floating point registers (gone at 3.7 GHz), then finally, integer instructions and registers.

Due to internal signal delays, the instructions should stop working in approximately the same order, regardless of the OC cooling and other factors.

Do you have any proof of this, or is this a question?

 

[Arcygenical]

I think he meant that as an example... Like, what the test suite would show.