Auer
[H]ard|Gawd
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NVIDIA Reportedly Using TSMC’s CoWoS
A new report coming from DigiTimes suggests that Nvidia is on the short list of customers that could be using TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) packaging for its upcoming GPUs.
TSMC’s CoWoS is a 2.5D packaging technology that packages multiple dies together at the wafer level on an interposer, something TSMC calls “wafer integration.” TSMC’s CoWoS has evolved to be able to target chips that far exceed the reticle limit, up to 2x reticle limit. TSMC and Broadcom recently illustrated this with the first 2x reticle limit interposer that will end up being used by Broadcom in HPC deployment. TSMC does this by essentially stitching interposers together at the wafer level and interconnecting them.
The benefits of CoWoS are improved interconnect performance and bandwidth, transistor density, and higher memory capacity -- TSMC’s current generation CoWoS currently supports up to six stacks of HBM.
As for what Nvidia would be targeting with TSMC’s current CoWoS is unknown. However, it’s worth noting Nvidia has used TSMC’s CoWoS packaging before on Pascal and Volta-based professional GPUs. It’s likely that Nvidia would be leveraging TSMC’s technology again for its upcoming Titan, Tesla, or Quadro cards -- presumably based on Ampere. But, we’ll see.
https://www.gamersnexus.net/news-pc/3563-hw-news-human-malware-vs-pc-amd-zen-vulnerability
A new report coming from DigiTimes suggests that Nvidia is on the short list of customers that could be using TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) packaging for its upcoming GPUs.
TSMC’s CoWoS is a 2.5D packaging technology that packages multiple dies together at the wafer level on an interposer, something TSMC calls “wafer integration.” TSMC’s CoWoS has evolved to be able to target chips that far exceed the reticle limit, up to 2x reticle limit. TSMC and Broadcom recently illustrated this with the first 2x reticle limit interposer that will end up being used by Broadcom in HPC deployment. TSMC does this by essentially stitching interposers together at the wafer level and interconnecting them.
The benefits of CoWoS are improved interconnect performance and bandwidth, transistor density, and higher memory capacity -- TSMC’s current generation CoWoS currently supports up to six stacks of HBM.
As for what Nvidia would be targeting with TSMC’s current CoWoS is unknown. However, it’s worth noting Nvidia has used TSMC’s CoWoS packaging before on Pascal and Volta-based professional GPUs. It’s likely that Nvidia would be leveraging TSMC’s technology again for its upcoming Titan, Tesla, or Quadro cards -- presumably based on Ampere. But, we’ll see.
https://www.gamersnexus.net/news-pc/3563-hw-news-human-malware-vs-pc-amd-zen-vulnerability