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“Finite element modeling has long been used to optimize package layouts, but it is now being employed at smaller scales to best understand how thin films will interact through processing and multiple thermal cycles.
To prevent wafer delamination during thinning processes stretching down to only 50 microns of silicon, three factors especially influence warpage — the die thickness remaining, high CTE mismatch, and high Young’s modulus, which induce more wafer bowing. Optimizing these parameters helps to prevent delamination during thinning.
Bonding techniques, including thermocompression bonding, reverse laser-assisted bonding, and a relatively new reverse thermocompression bonding (R-LTC), may all be considered in advanced packaging. R-LTC may offer better alignment and lower standoff thickness, important issues in multi-chip packaging.
Warpage has and will require control measures during assembly, including reflow tooling selection, as well as selecting compatible CTE materials and only gradual CTE changes in the stack. Novel materials with low CTE and low Young’s modulus help improve wafer and die bowing.”
Source: https://semiengineering.com/mitigating-warpage-in-multi-chiplet-systems/
To prevent wafer delamination during thinning processes stretching down to only 50 microns of silicon, three factors especially influence warpage — the die thickness remaining, high CTE mismatch, and high Young’s modulus, which induce more wafer bowing. Optimizing these parameters helps to prevent delamination during thinning.
Bonding techniques, including thermocompression bonding, reverse laser-assisted bonding, and a relatively new reverse thermocompression bonding (R-LTC), may all be considered in advanced packaging. R-LTC may offer better alignment and lower standoff thickness, important issues in multi-chip packaging.
Warpage has and will require control measures during assembly, including reflow tooling selection, as well as selecting compatible CTE materials and only gradual CTE changes in the stack. Novel materials with low CTE and low Young’s modulus help improve wafer and die bowing.”
Source: https://semiengineering.com/mitigating-warpage-in-multi-chiplet-systems/