Mega Transfers per Second

[getnate]

Intel processors show the front side bus speed in MegaTransfers per second, why does it appear to be 4x the actual FSB frequency? 2x would make sense because of DDR but why 4x?

For example: The Core2Duo 6850 (3.0ghz) shows 1333 MT/s, but the multiplier is 9x which indicates the actual FSB speed is 333mhz. The MT/s is 4x the actual FSB.
Source: http://en.wikipedia.org/wiki/List_of_Intel_Core_2_microprocessors#Core_2_Duo

-Nate

 

[Menelmarar]

Quad pumped FSB. Intel has been using this design sine the original P4 days. It's not related to the memory.

So for a 1333MHz (or 1333MT/s) the base FSB clock is 333.25MHz. The cpu clock multiplier is locked at 9x. So there you have 333.25 * 9x multiplier = 3.0 GHz CPU.

Now I'm going to back peddle to confuse you. Even though it is unrelated to DDR, it works on the same principal. Both are making more than one transfer per clock cycle. When it's double data rate like for DDR memory, data is transferred on the peak and the trough of the waveform. For quad data rate like a quad-pumped FSB, the data is send on the peak, the trough, and both zero crossings.