• Some users have recently had their accounts hijacked. It seems that the now defunct EVGA forums might have compromised your password there and seems many are using the same PW here. We would suggest you UPDATE YOUR PASSWORD and TURN ON 2FA for your account here to further secure it. None of the compromised accounts had 2FA turned on.
    Once you have enabled 2FA, your account will be updated soon to show a badge, letting other members know that you use 2FA to protect your account. This should be beneficial for everyone that uses FSFT.

Leaked AMD's dual V-Cache will be the Ryzen 9 9950X3D2

would be a bit like those 3800xt/5800xt product they did I guess, but a new naming scheme because 9800xt3d did not sounded right to them.
 
Haven't there been rumors and leaks about a dual CCD 3DCache chip several times in the 7000 and 9000 series thus far? I mean, I hope its accurate this time given that homogeneous cache not only benefits certain workloads but also avoids all the issues of heterogeneous cache cores (relying on Xbox Game Bar to assign core usage, scheduler issues etc), but we've been here before.
 
El_Capitan said:
I'm surprised they don't put in a V-Cache just for NPU's...
Click to expand...
They are too small; it would be cheaper to add the cache to the NPU itself and make it a little bit larger than to go through the process of stacking them.
 
Also AI workload tend to be large quantity of fresh flow of new data/one pass that do not benefit a lot from cache, there is a reason bandwith is so important
 
What I want to see is a 6-core, 12-thread, x3D Cache APU, bundled with something like the 860S with a TDP between 120W and 170W that preferably has functioning support for CUDIMM modules, not just a pass-through mode.

I think that would make a brutal tiny PC.
 
cudimm support from AMD would be nice. Not sure where that is on their roadmap though.
 
Lakados said:
What I want to see is a 6-core, 12-thread, x3D Cache APU, bundled with something like the 860S with a TDP between 120W and 170W that preferably has functioning support for CUDIMM modules, not just a pass-through mode.

I think that would make a brutal tiny PC.
Click to expand...
The issue there is that you'd get 99% the performance of a 9800x3d and AMD couldn't charge more for it, so it would probably lose them money.
 
RanceJustice said:
Haven't there been rumors and leaks about a dual CCD 3DCache chip several times in the 7000 and 9000 series thus far? I mean, I hope its accurate this time given that homogeneous cache not only benefits certain workloads but also avoids all the issues of heterogeneous cache cores (relying on Xbox Game Bar to assign core usage, scheduler issues etc), but we've been here before.
Click to expand...
No dual v-cache CPU will have a homogenous v-cache; it'll be two independent v-caches under each CCD if it is made. That means you will still run into the issue of preventing threads from hopping CCDs as transferring data across will cause stuttering, necessitating OS level software fixes. The only thing workloads a chip like this would benefit are certain types of workstation and database programs. Otherwise, there is no point to getting this over a 9950X3D.
 
Tsumi said:
No dual v-cache CPU will have a homogenous v-cache; it'll be two independent v-caches under each CCD if it is made. That means you will still run into the issue of preventing threads from hopping CCDs as transferring data across will cause stuttering, necessitating OS level software fixes. The only thing workloads a chip like this would benefit are certain types of workstation and database programs. Otherwise, there is no point to getting this over a 9950X3D.
Click to expand...
I've heard this time and time again, and on the surface it makes sense, but scheduling is far from perfect, and I imagine there are a LOT of game threads that get shunted to another CCD, aside from the inter CCD latency, threads would perform MUCH better than the alternative in the very common event of a thread jumping to the secondary CCD. so I imagine the performance profile of a dual X3D 2CCD chip versus a single X3D 2CCD chip is "it performs either the exact same or better, never worse"

So a small but abject improvement.
 
Lakados said:
They could gimp the PCIe lanes or something...
Click to expand...
Don't give them ideas, AM5 boards already suck in terms of PCIe lane count and slot layout, presumably because it makes upselling Threadripper that much easier.

Gah, how much I'd like to have a V-Cache-on-every-CCD Shimada Peak chip... doesn't even have to have the expected Threadripper core count, I just want I/O that isn't crap.
 
Tsumi said:
No dual v-cache CPU will have a homogenous v-cache; it'll be two independent v-caches under each CCD if it is made. That means you will still run into the issue of preventing threads from hopping CCDs as transferring data across will cause stuttering, necessitating OS level software fixes. The only thing workloads a chip like this would benefit are certain types of workstation and database programs. Otherwise, there is no point to getting this over a 9950X3D.
Click to expand...
When I say homogeneous I mean that the OS will not have to deal with "Some cores on one CCD with lower turbo clock speed maximums and extra Vcache" vs "Some cores on another CCD with higher clock speed maximums yet no Vcache" . As we saw with Microsoft first with the P an E core stuff, this took both the ThreadDirector2 update to even be viable even with Intel's on-die governors, and when the cache started with 2CCD AMD X3D CPUs, instead of advanced CPU firmware, mobo firmware, or even driver based profiling and the like it seems left up primarily to the OS, which became the "If Xbox Game Bar says its a game, then CCD0, the one with the cache" was as complex as it got at least at the start. I admit I may be missing something now, but there were considerable issues especially if you didn't have Win11 depending on what you were running. Linux, by virtue of how its scheduler works a bit differently, seemed to do better overall but still had to deal with the heterogeneous nature of the different cores with different clock speed maxes and different cache.

Even if its 2 independent Vcaches, in that they won't interact between CCDs or be one big shared one, it still means that the issue comes down to jumping between identical cores on 'both sides' , which is less complex a fix vs having to account for some cores have less cache and others have higher frequencies.

NamelessPFG said:
Don't give them ideas, AM5 boards already suck in terms of PCIe lane count and slot layout, presumably because it makes upselling Threadripper that much easier.

Gah, how much I'd like to have a V-Cache-on-every-CCD Shimada Peak chip... doesn't even have to have the expected Threadripper core count, I just want I/O that isn't crap.
Click to expand...
I've long advocated that just like how Ryzen moved up to supporting 12 and even 16 Cores, especially if Threadripper is no longer the "mixed use gaming enthusiast creative server" of the X399 era or the parallels on the Intel side now non-existant, then AMD should ensure that higher versions of Ryzen chipsets like X670E / X870E etc... could have the option of up to quad-channel RAM and a ton more PCI-E lanes (ideally accompanied by more PCI-E slots too).. We're in an era where more "regulat users" than ever can be starved for lanes because of M.2 drives, and you can end up keeping your GPU from running at full x16 speeds (putting aside you're lucky to get 2x full sized slots these days and neither of them can run at both x16, instead dropping down to x8/x8 at max if both populated and if you use a M.2 slot somewhere the second slot drops down to x4) I cant see why there hasn't been progress. Alternately, Threadripper has seemed to move farther and farther to the "Workstation and Server JR , heavily parallelized usages only + a giant CPU and platform cost" side so its not like buying a $2000+ CPU can even get paralell single core performance, gaming capability with 3D Cache etc... so it feels like a waste unless you're entirely purpose built, unlike the HEDT glory days of the past when it did everything the mainstream platform did equal, often better, plus more features and enhanced I/O etc
 
El_Capitan said:
Yeah, basically the 9800X3D with a higher boost clock. Doesn't make sense to me. 🤷‍♀️🤷‍♂️
Click to expand...
A binned single CCD that can sustain a much higher boost and all-core boost would actually be very good for the release and add an extra 5% to Zen 5's pejorative Zen 5% moniker.

RanceJustice said:
Haven't there been rumors and leaks about a dual CCD 3DCache chip several times in the 7000 and 9000 series thus far? I mean, I hope its accurate this time given that homogeneous cache not only benefits certain workloads but also avoids all the issues of heterogeneous cache cores (relying on Xbox Game Bar to assign core usage, scheduler issues etc), but we've been here before.
Click to expand...
I've wanted a dual CCD 3d Vcache chip since Zen 3 when it was first teased, and bought a TechN waterblock for the intended build. Fortunately, I was able to cycle it into a Zen 4 7950x build. Having dual v cache, especially with a binned chip that boosts higher is what I wanted from the get go to avoid all scheduling and parking issues for Zen 3, Zen 4, and now Zen 5. However since I did eventually buy a 9950X3D, I likely won't be making the upgrade, but will probably transfer over to a Zen6X3D2 should it come out.
 
NamelessPFG said:
Don't give them ideas, AM5 boards already suck in terms of PCIe lane count and slot layout, presumably because it makes upselling Threadripper that much easier.

Gah, how much I'd like to have a V-Cache-on-every-CCD Shimada Peak chip... doesn't even have to have the expected Threadripper core count, I just want I/O that isn't crap.
Click to expand...
They already only use 16 total PCIe lanes on their mobile chips.
4 for the chipset, 4 for storage, 8 for attached GPU or Other. Putting the APU’s into this category wouldn’t be the end of the world.
 
RanceJustice said:
When I say homogeneous I mean that the OS will not have to deal with "Some cores on one CCD with lower turbo clock speed maximums and extra Vcache" vs "Some cores on another CCD with higher clock speed maximums yet no Vcache" . As we saw with Microsoft first with the P an E core stuff, this took both the ThreadDirector2 update to even be viable even with Intel's on-die governors, and when the cache started with 2CCD AMD X3D CPUs, instead of advanced CPU firmware, mobo firmware, or even driver based profiling and the like it seems left up primarily to the OS, which became the "If Xbox Game Bar says its a game, then CCD0, the one with the cache" was as complex as it got at least at the start. I admit I may be missing something now, but there were considerable issues especially if you didn't have Win11 depending on what you were running. Linux, by virtue of how its scheduler works a bit differently, seemed to do better overall but still had to deal with the heterogeneous nature of the different cores with different clock speed maxes and different cache.

Even if its 2 independent Vcaches, in that they won't interact between CCDs or be one big shared one, it still means that the issue comes down to jumping between identical cores on 'both sides' , which is less complex a fix vs having to account for some cores have less cache and others have higher frequencies.


I've long advocated that just like how Ryzen moved up to supporting 12 and even 16 Cores, especially if Threadripper is no longer the "mixed use gaming enthusiast creative server" of the X399 era or the parallels on the Intel side now non-existant, then AMD should ensure that higher versions of Ryzen chipsets like X670E / X870E etc... could have the option of up to quad-channel RAM and a ton more PCI-E lanes (ideally accompanied by more PCI-E slots too).. We're in an era where more "regulat users" than ever can be starved for lanes because of M.2 drives, and you can end up keeping your GPU from running at full x16 speeds (putting aside you're lucky to get 2x full sized slots these days and neither of them can run at both x16, instead dropping down to x8/x8 at max if both populated and if you use a M.2 slot somewhere the second slot drops down to x4) I cant see why there hasn't been progress. Alternately, Threadripper has seemed to move farther and farther to the "Workstation and Server JR , heavily parallelized usages only + a giant CPU and platform cost" side so its not like buying a $2000+ CPU can even get paralell single core performance, gaming capability with 3D Cache etc... so it feels like a waste unless you're entirely purpose built, unlike the HEDT glory days of the past when it did everything the mainstream platform did equal, often better, plus more features and enhanced I/O etc
Click to expand...
Unfortunately giving consumers those options detracts from sales of subscription based cloud services and blah blah blah.

I’d be far happier with better bifurcation options, exceedingly few consumer options can make use of 16 PCIe5 lanes. I think it’s better if things were scaled back to make better use of the bandwidth that’s there and not arbitrary waste the limited lanes.

Hell Is be happy if they brought back daughter boards.

I doubt that we’re going to get platforms with more anything, anytime soon. So it’d settle with the ability to make better use of less.
 
El_Capitan said:
Yeah, basically the 9800X3D with a higher boost clock. Doesn't make sense to me. 🤷‍♀️🤷‍♂️
Click to expand...
Probably to have something to respond to Intel's upcoming chip. They aren't ready with a new generation yet, and even if the 9800X3D is perfectly competitive there's always this "but I want something new" thing from consumers so they up the boost clock, change the name, and there you go "new" chip to sell that is probably perfectly competitive.
 
My 9950X3D will serve me just fine till Zen 6. Considering we will be getting a core jump to 24 for Z6, and 32 for Z7...Will make these refreshed models less desirable imo. But then again only so for people in the know...Can still see these all selling well...lol.
 
Lakados said:
Unfortunately giving consumers those options detracts from sales of subscription based cloud services and blah blah blah.

I’d be far happier with better bifurcation options, exceedingly few consumer options can make use of 16 PCIe5 lanes. I think it’s better if things were scaled back to make better use of the bandwidth that’s there and not arbitrary waste the limited lanes.

Hell Is be happy if they brought back daughter boards.

I doubt that we’re going to get platforms with more anything, anytime soon. So it’d settle with the ability to make better use of less.
Click to expand...
Funny that you mention daughterboards, because it used to be that storage used to be added with "hard cards" that had both a disk controller and space to mount a 3.5" hard drive.

PCIe to M.2 or U.2/U.3 drive adapters would be the modern equivalent, and while many such accessories exist, the cheap ones need bifurcation in x4 multiples (easily done on my X399 Threadripper, but my Intel Z690 and W680 boards don't allow it), and adding a PLX switch to negate the need for that drives the price up substantially, like "$800 for a Sonnet octo-M.2 adapter card, drives not included" expensive.

I'd rather have more PCIe slots and adapter cards to add M.2s, rather than the current approach of lots of M.2s and piss all for PCIe slots, but I understand why they do this - it's because comically thick 4-slot GPUs are becoming normalized now, and M.2 slots could just slip under those.

Part of it's because it's not just NVMe drives (and maybe SAS controllers for spinning rust hard drives) that need PCIe lanes. Want 10Gb, 25Gb, 40Gb, maybe even 100Gb networking? That eats up PCIe lanes fast, especially with cheaper 10Gb NICs being PCIe 2.0 x8 designs cast off from the enterprise/datacenter space. Multichannel video capture, maybe even with 4K inputs? That's another x4 lanes needed, easily.
 
NamelessPFG said:
Funny that you mention daughterboards, because it used to be that storage used to be added with "hard cards" that had both a disk controller and space to mount a 3.5" hard drive.

PCIe to M.2 or U.2/U.3 drive adapters would be the modern equivalent, and while many such accessories exist, the cheap ones need bifurcation in x4 multiples (easily done on my X399 Threadripper, but my Intel Z690 and W680 boards don't allow it), and adding a PLX switch to negate the need for that drives the price up substantially, like "$800 for a Sonnet octo-M.2 adapter card, drives not included" expensive.

I'd rather have more PCIe slots and adapter cards to add M.2s, rather than the current approach of lots of M.2s and piss all for PCIe slots, but I understand why they do this - it's because comically thick 4-slot GPUs are becoming normalized now, and M.2 slots could just slip under those.

Part of it's because it's not just NVMe drives (and maybe SAS controllers for spinning rust hard drives) that need PCIe lanes. Want 10Gb, 25Gb, 40Gb, maybe even 100Gb networking? That eats up PCIe lanes fast, especially with cheaper 10Gb NICs being PCIe 2.0 x8 designs cast off from the enterprise/datacenter space. Multichannel video capture, maybe even with 4K inputs? That's another x4 lanes needed, easily.
Click to expand...
More PCIe lanes would be fantastic, but the costs associated with them are just too high.

On the CPU’s they require a lot of pins, and on the boards they need a lot of insulation and noise cancelation. All things that are counter productive to cost reduction, so as much as I want more lanes, unless some dramatic shift in design and execution comes out of the blue I just don’t see it happening.

I’d love a control card you could slot into a 16 pin PCIe5 slot that was eATX sized minus a cutout for an ITX board. So it could fit into existing cases with relative ease.

Plug it into the 16 slot PCIe port and the big board was just loaded in PCIe ports you could bifurcate as needed as PCIe versions 3-5.
Just be “this is your total lane count” and as you divide them up it just subtracts them accordingly.
 
if they start making more 5.0 x1, x2 device, we would not necessarily feel a lack of PCIe lanes, 4GB/s (8GB in both direction combined at the same time) is already a lot, 3.0x4 was good for a lot of stuff and still is.

5.0x1 That fast enough for 30Gb/s Ethernet (x2 for 60GB/s), 5.0x1 is quite a lot for an NVME drive, sustain 4GB/s (8gb if you copy and paste at the same time) and that more than fast enough for virtually everything. x8 pci 5.0 for the GPU will also tend to work, if the CPU-Mobo give you 10 others fully free, that 30gbs/ethernet, 6 x m2 and still a lot of bandwidth left.
 
Last edited:
Lakados said:
I’d love a control card you could slot into a 16 pin PCIe5 slot that was eATX sized minus a cutout for an ITX board. So it could fit into existing cases with relative ease.

Plug it into the 16 slot PCIe port and the big board was just loaded in PCIe ports you could bifurcate as needed as PCIe versions 3-5.
Click to expand...
I'd be happy with just a bit more bifurcation on regular motherboards. So many these days seem to be x16 or x8/x4/x4, why can't I have x8/x8, or x8/x4/x1^4 etc?
 
I would have bought one if they released it earlier since I already have a 9950x3d, but at this point, I'll wait for the zen6 version.
 
NamelessPFG said:
Funny that you mention daughterboards, because it used to be that storage used to be added with "hard cards" that had both a disk controller and space to mount a 3.5" hard drive.

PCIe to M.2 or U.2/U.3 drive adapters would be the modern equivalent, and while many such accessories exist, the cheap ones need bifurcation in x4 multiples (easily done on my X399 Threadripper, but my Intel Z690 and W680 boards don't allow it), and adding a PLX switch to negate the need for that drives the price up substantially, like "$800 for a Sonnet octo-M.2 adapter card, drives not included" expensive.

I'd rather have more PCIe slots and adapter cards to add M.2s, rather than the current approach of lots of M.2s and piss all for PCIe slots, but I understand why they do this - it's because comically thick 4-slot GPUs are becoming normalized now, and M.2 slots could just slip under those.

Part of it's because it's not just NVMe drives (and maybe SAS controllers for spinning rust hard drives) that need PCIe lanes. Want 10Gb, 25Gb, 40Gb, maybe even 100Gb networking? That eats up PCIe lanes fast, especially with cheaper 10Gb NICs being PCIe 2.0 x8 designs cast off from the enterprise/datacenter space. Multichannel video capture, maybe even with 4K inputs? That's another x4 lanes needed, easily.
Click to expand...
Lakados said:
More PCIe lanes would be fantastic, but the costs associated with them are just too high.

On the CPU’s they require a lot of pins, and on the boards they need a lot of insulation and noise cancelation. All things that are counter productive to cost reduction, so as much as I want more lanes, unless some dramatic shift in design and execution comes out of the blue I just don’t see it happening.

I’d love a control card you could slot into a 16 pin PCIe5 slot that was eATX sized minus a cutout for an ITX board. So it could fit into existing cases with relative ease.

Plug it into the 16 slot PCIe port and the big board was just loaded in PCIe ports you could bifurcate as needed as PCIe versions 3-5.
Just be “this is your total lane count” and as you divide them up it just subtracts them accordingly.
Click to expand...
Some good ideas - being able to take advantage of bifurcation properly and without a rat's nest would be helpful. Daughterboards and awareness of the lanes available vs any particular device's needs , easily displayed on the BIOS/UEFI so users can get an idea of their options etc.

Of course, the whole thing about cost , while probably true, really frustrates me as I'm talking about AM5 CPU boards that are roughly $600+ for the high end variants of X670E / X870E, they can't be scrabbling for cost cutting and expecting enthusiasts to just assume they're a poor small company trying to make ends meet. They could easily make the adaptations for the higher end of the B850 / X870 / X870E etc.. to ensure it has options for more lanes provided you have a CPU that supports them (as well as the more advanced chipsets could be configured with more chipset lanes). I remember my X99 had the difference between the 5820K which had limited PCI-E lanes, vs the 5930K and 5060X which had the full compliment - maybe they could do something like that and give people yet another reason to step up to higher tier CPUs. Same thing with RAM channels - I can recall how Intel boards during the DDR4/DDR5 switch paid a little extra and had versions of Z690 so you could choose a board that was DDR4 compatible or the new DDR5. Maybe it would be even easier to set up dual channel on everything, and quad channel on some chipsets. It seems like AMD is leaving money on the table by refusing to either overhaul Ryzen to make it capable of wider usecases or give Threadripper the kind of features that would allow it to be universally viable for the money spent, even at gaming workloads and enthusiast capabilities.

I don't mind paying more for quality, features, and versatility but it gets annoying to see prices continue to climb yet companies claim they have no choice to either lower prices or increase features/value for the continually rising prices.
 

"AMD Ryzen 9 9950X3D2 and Ryzen 7 9850X3D are Real, Coming this CES?​

by btarunr Today, 07:11 Discuss (17 Comments)
AMD is preparing to refresh its Ryzen 9000 series "Zen 5" desktop processor lineup with two high-end chips targeting gamers and PC enthusiasts, the 8-core Ryzen 7 9850X3D, and the 16-core Ryzen 9 9950X3D2. The 9850X3D is a speed-bumped 9800X3D, while the 9950X3D2 comes with 3D V-Cache on both its 8-core chiplets, compared to the 9950X3D, which only has it on one of its chiplets. The Ryzen 7 9850X3D comes with a maximum turbo frequency of 5.60 GHz, a 400 MHz increase over the 9800X3D, along with a TDP of 120 W, which is expected to increase its single-thread performance by 5-7%.

The Ryzen 9 9950X3D2 is a different beast. It comes with a maximum boost frequency of 5.60 GHz, which is a 100 MHz reduction over the 5.70 GHz that the 9950X3D comes with, but both its chiplets have 3D V-Cache, allowing for more flexible scheduling and thread migration. With a combined L3 cache of 192 MB, this chip could also be vastly preferred by the workstation and creator crowd that's working on memory-intensive workloads. All this comes at a cost, though, with AMD rumored to increase TDP to 200 W, up from the 170 W of the 9950X3D, which could mean a PPT value nearing the 250 W-mark. Geekbench and PassMark numbers of the 9950X3D2 just surfaced on the web, which show the newer chip to be 2% faster than the 9950X3D despite the marginally lower clock speed, however, the real heft of this chip will be felt in memory/cache sensitive workloads."

1766778233060.png
 
If this actually comes at a reasonable price and ideally swiftly after CES, I may consider an upgrade for the 9950X3D2 from my current 7950X3D. The 9000 series improvements overall, the bump in boost frequency shared on all cores ( 7950X3D had a 5.2ghz hard cap on the cache CCD, where the other could hit the higher frequencies) However, I do have to wonder why they've taken such a long time to debut these? They already missed the holiday season, and depending on when Zen 6 (and for that matter, Intel's next generation competitor who's name I forget but is supposed to be well..more competitive) arrives, many users may prefer to just wait instead.
 
RanceJustice said:
If this actually comes at a reasonable price and ideally swiftly after CES, I may consider an upgrade for the 9950X3D2 from my current 7950X3D. The 9000 series improvements overall, the bump in boost frequency shared on all cores ( 7950X3D had a 5.2ghz hard cap on the cache CCD, where the other could hit the higher frequencies) However, I do have to wonder why they've taken such a long time to debut these? They already missed the holiday season, and depending on when Zen 6 (and for that matter, Intel's next generation competitor who's name I forget but is supposed to be well..more competitive) arrives, many users may prefer to just wait instead.
Click to expand...
9950X3D MSRP is $700 and is currently hovering around $675 retail. 9950X MSRP was $650 and is currently hovering around $550. I would expect the 9950X3D2 to be around $900, if not initially starting out at $1000 for that halo product price point.

Zen 6 will most likely be mid-late 2026 based on the lack of leaks so far. In any case, the X3D chips will be about a year behind the initial launch, so they shouldn't impact these sales. As for the delay, it's probably the simple answer- yields. Yields weren't good enough to produce higher clocked X3D chips to fulfill demand. The slower ones got shoved into the 9800X3D while the faster ones went in the 9950X3D. Now they probably have enough 5.6 ghz capable CCDs to fulfill potential 9850X3D and 9950X3D2 demand. Although that demand is likely would have dropped some due to the RAM apocalypse.
 
erek said:

"AMD Ryzen 9 9950X3D2 and Ryzen 7 9850X3D are Real, Coming this CES?​

by btarunr Today, 07:11 Discuss (17 Comments)
AMD is preparing to refresh its Ryzen 9000 series "Zen 5" desktop processor lineup with two high-end chips targeting gamers and PC enthusiasts, the 8-core Ryzen 7 9850X3D, and the 16-core Ryzen 9 9950X3D2. The 9850X3D is a speed-bumped 9800X3D, while the 9950X3D2 comes with 3D V-Cache on both its 8-core chiplets, compared to the 9950X3D, which only has it on one of its chiplets. The Ryzen 7 9850X3D comes with a maximum turbo frequency of 5.60 GHz, a 400 MHz increase over the 9800X3D, along with a TDP of 120 W, which is expected to increase its single-thread performance by 5-7%.

The Ryzen 9 9950X3D2 is a different beast. It comes with a maximum boost frequency of 5.60 GHz, which is a 100 MHz reduction over the 5.70 GHz that the 9950X3D comes with, but both its chiplets have 3D V-Cache, allowing for more flexible scheduling and thread migration. With a combined L3 cache of 192 MB, this chip could also be vastly preferred by the workstation and creator crowd that's working on memory-intensive workloads. All this comes at a cost, though, with AMD rumored to increase TDP to 200 W, up from the 170 W of the 9950X3D, which could mean a PPT value nearing the 250 W-mark. Geekbench and PassMark numbers of the 9950X3D2 just surfaced on the web, which show the newer chip to be 2% faster than the 9950X3D despite the marginally lower clock speed, however, the real heft of this chip will be felt in memory/cache sensitive workloads."

View attachment 775174
Click to expand...

These appearances suggest that either the CPUs have started to be shipped off to reviewers, or that motherboard vendors are testing these to configure the BIOS for launch

Keep in mind that PassMark listings can be fabricated, so take all this with a heavy grain of salt.


AMD's dual-cache Ryzen 9 9950X3D2 appears in first benchmark leaks — gaming-focused CPU features 192MB of L3 cache stacked across both CCDs​

News
By Hassam Nasir published 23 hours ago
Early numbers paint an amicable picture.

https://www.tomshardware.com/pc-com...es-192mb-of-l3-cache-stacked-across-both-ccds
 
El_Capitan said:
Yeah, basically the 9800X3D with a higher boost clock. Doesn't make sense to me. 🤷‍♀️🤷‍♂️
Click to expand...

If they’ve matured their manufacturing process enough to net good yields at the higher speed, why not? It may not make sense for people already on a 9800x3d, but if you even take a peek outside that bubble you’ll see not everyone is running a 9800x3d.

I myself have been eyeing a CPU upgrade to the gaming box I have at my parents house currently flaunting a 5700x. This news along with the AM5+32GB DDR5 6000 CL30 combo I found around the same time (for less that price of ram alone) was just the catalyst I needed to pull the trigger.
 
RanceJustice said:
Haven't there been rumors and leaks about a dual CCD 3DCache chip several times in the 7000 and 9000 series thus far? I mean, I hope its accurate this time given that homogeneous cache not only benefits certain workloads but also avoids all the issues of heterogeneous cache cores (relying on Xbox Game Bar to assign core usage, scheduler issues etc), but we've been here before.
Click to expand...

It’s still two CCDs though so you’d still need gamebar to keep the game processes on one CCD and avoid the latency hit. The plus side is on those occasions where gamebar doesn’t work, the penalty should be less and would be especially beneficial on games that scale past 8 cores. Ultimately until we get 12+ core CCDs, you’ll still need gamebar for optimal core assignment.
 
Tsumi said:
9950X3D MSRP is $700 and is currently hovering around $675 retail. 9950X MSRP was $650 and is currently hovering around $550. I would expect the 9950X3D2 to be around $900, if not initially starting out at $1000 for that halo product price point.

Zen 6 will most likely be mid-late 2026 based on the lack of leaks so far. In any case, the X3D chips will be about a year behind the initial launch, so they shouldn't impact these sales. As for the delay, it's probably the simple answer- yields. Yields weren't good enough to produce higher clocked X3D chips to fulfill demand. The slower ones got shoved into the 9800X3D while the faster ones went in the 9950X3D. Now they probably have enough 5.6 ghz capable CCDs to fulfill potential 9850X3D and 9950X3D2 demand. Although that demand is likely would have dropped some due to the RAM apocalypse.
Click to expand...
When it comes to yields for the current X3D cache chips / X3D2, is that really what you think has been holding them back? I'd think they'd have enough of them for both core usage earlier on as they'd only need to divert a percentage of those from the 9950X3D. Had they done this earlier I'm sure they would have gotten users paying for the upgrade the 9950X3D2 had it been available , but now so many users are probably on their existing 9950X3D if they wanted them. Outside of those still on 7000 series or who have 1 CCD chips who are more likely to upgrade, it seems that the market is comparatively small this late to be worried about not cannibalizing 'standard' 9950X3D capable cores to put them into a chip with 2 of them. I wasn't under the impression that the yields were so small at this time or the process so new that they had to make those kinds of decision (where of course the 'big' stuff is going for Epyc and the like. Hell, I'm still annoyed that TR doesn't have X3D options when Epyc does last I checked; there are rumors from late 2024 about 3D cache coming to TR in 2025 but that didn't seem to happen)

Zen6 X3D chips coming 6mo - 1yr later in 2027? I could understand the delay in the 5000 series where the process was new and even the 7000 series with its new bonding of the cache, but with the 9000 and whatever the Zen6 generation will be named they have to know that the vast majority of enthusiasts are going to be waiting to buy the X3D version since the cache has benefit to gaming and other workloads. Especially if Nova Lake or whatever the next Intel platform turns out to be more competitive, I'm not sure that AMD will want to leave that kind of delay unless they were forced to do so?

WilyKit said:
It’s still two CCDs though so you’d still need gamebar to keep the game processes on one CCD and avoid the latency hit. The plus side is on those occasions where gamebar doesn’t work, the penalty should be less and would be especially beneficial on games that scale past 8 cores. Ultimately until we get 12+ core CCDs, you’ll still need gamebar for optimal core assignment.
Click to expand...
With symmetrical cache and clock/boost maxes I imagine that it will somewhat naturally trend towards one CCD for a single program (except in the cases of a game that spawns processes that would eclipse 8c / 16t of a single CCD, which are somewhat rare), as it won't be an issue of the system being 'pulled' to the higher clocking cacheless cores on the other CCD like in the asymmetric arrangement. I agree that in circumstances where they are spread across both CCDs there may still be a latency hit (albeit a smaller penalty as you mentioned) but I imagine most of those circumstances will be applications that can max out all the cores an threads on one CCD and move to the other, as opposed to the "picking and choosing" that the game bar served, bluntly as it may have worked, to prevent. Though scheduler improvements of all sorts, enhanced governors and better hardware/firmware elements, will be worthwhile along the way.
 
You must log in or register to reply here.
Back
Top