Intel with XDR?

[shawmanus]

Is there any chance that intel would release XDR based chipsets for 45nm core shrink. This is being speculated by TheInq which I know is not too reliable. But I hope it is true.
If Intel can offer both XDR and DDR3 as options it would be great.

http://www.theinquirer.net/default.aspx?article=34383

Can Poncho or some other intel employee comment on this article.

 

[D4hPr0]

Dont you think Intel had enough of Rambust???

 

[Duke3d87]

being that it has the potential of 100 GB/sec ish in dual channel i would say no...

and it wasn't rambus' fault, it was the other companies that price fixed itl

 

[shawmanus]

Dont you think Intel had enough of Rambust???

I mentioned both XDR and DDR3. Its always good for consumers to have all the choices. Last time Intel launched PIV with only RDRAM which was overpriced and hence it was a bad choice. XDR2 seems to have way more bandwidth than RDRAM. It should be very useful for XE quad core or servers.

 

[eno-on]

No, not gonna happen.
Requires completely different northbridge, why bother?

 

[Duke3d87]

No, not gonna happen.
Requires completely different northbridge, why bother?

becuase it solves a lot of their bandwith problems? You can have dual channel XDR RAM and have enough bandwith for an 8 way tigerton system pretty easily.

 

[Donnie27]

being that it has the potential of 100 GB/sec ish in dual channel i would say no...

and it wasn't rambus' fault, it was the other companies that price fixed itl

Were'd you see that? I thought they were talking about 33.2GB or about 4 X 8.4GB?

You're absolutely right though, it wasn't RAMBUS's fault and both Infineon and Corsair were caught

 

[Donnie27]

I mentioned both XDR and DDR3. Its always good for consumers to have all the choices. Last time Intel launched PIV with only RDRAM which was overpriced and hence it was a bad choice. XDR2 seems to have way more bandwidth than RDRAM. It should be very useful for XE quad core or servers.

It was overpriced because they were locked out by every one of the manufacturers except Samsung. You can spread the costs if only one manufacturer and Intel have to all of the legwork. The funniest thing of all is that Intel would then bail out Micron, Hynix and the others. They spent about 1 BILLION on the RAM makers Hell, they even sent out engineers to help with DDR3200 and get DDR2 started. They're bad guys?

 

[eno-on]

becuase it solves a lot of their bandwith problems? You can have dual channel XDR RAM and have enough bandwith for an 8 way tigerton system pretty easily.

Not without an on die memory controller, it doesn't.

 

[Duke3d87]

Were'd you see that? I thought they were talking about 33.2GB or about 4 X 8.4GB?

You're absolutely right though, it wasn't RAMBUS's fault and both Infineon and Corsair were caught

The other article that the INQ linked to said that each chip was 16 bit @ 3.2 GHz

So, according to Charlie

2*3.2 GHz = 6.4 GB/sec (per chip) * 8 (8 chips/module) = 51.2 GB/sec

and if it does dual channel, it would be 102.4 GB/sec

Not without an on die memory controller, it doesn't.

It actually does although it's not ideal.

Right now the current setup for XeonDP is quad channel FBDIMM. FBDIMM is expensive, costs a lot, puts out a lot of power and has a higher latency. They have to put it in quad channel for memory throughput.

With the XeonMP, the last time i checked, they had one main controller and several sub controllers. IF Intel went to XDR and the bandwith that Charlie posted is correct, you can get a lot more bandwith with less latency, power, heat and cost.

I could be completely wrong and i'm waiting for Poncho to tell me so

 

[duby229]

The other article that the INQ linked to said that each chip was 16 bit @ 3.2 GHz

So, according to Charlie

2*3.2 GHz = 6.4 GB/sec (per chip) * 8 (8 chips/module) = 51.2 GB/sec

and if it does dual channel, it would be 102.4 GB/sec


It actually does although it's not ideal.

Right now the current setup for XeonDP is quad channel FBDIMM. FBDIMM is expensive, costs a lot, puts out a lot of power and has a higher latency. They have to put it in quad channel for memory throughput.

With the XeonMP, the last time i checked, they had one main controller and several sub controllers. IF Intel went to XDR and the bandwith that Charlie posted is correct, you can get a lot more bandwith with less latency, power, heat and cost.

I could be completely wrong and i'm waiting for Poncho to tell me so

Which will still have to be funnelled through a piddly 1333 FSB which is somewhere right around 10GB/s then that has to be shared between cores, so you'll only get about 2.5 GB/s per core...

So ya see it really doesnt matter untill Intel does something about the buss..

Besides your math is faulty... It would be correct if each chip was serial with a DDR signal. But it's not.... It's 16bit chips. at 3.2 Ghz on a shared buss... The buss is prolly DDR. or some derivitive.

soooo 16bits x 3.2 x ddr equals 102.4 GB/s second per dimm.

 

[Duke3d87]

Which will still have to be funnelled through a piddly 1333 FSB which is somewhere right around 10GB/s then that has to be shared between cores, so you'll only get about 2.5 GB/s per core...

So ya see it really doesnt matter untill Intel does something about the buss..

Besides your math is faulty... It would be correct if each chip was serial with a DDR signal. But it's not.... It's 16bit chips. at 3.2 Ghz on a shared buss... The buss is prolly DDR. or some derivitive.

soooo 16bits x 3.2 x ddr equals 102.4 GB/s second per dimm.

wait, isn't that what i said?

http://www.theinquirer.net/default.aspx?article=18371

 

[Donnie27]

The other article that the INQ linked to said that each chip was 16 bit @ 3.2 GHz

So, according to Charlie

2*3.2 GHz = 6.4 GB/sec (per chip) * 8 (8 chips/module) = 51.2 GB/sec

and if it does dual channel, it would be 102.4 GB/sec


It actually does although it's not ideal.

Right now the current setup for XeonDP is quad channel FBDIMM. FBDIMM is expensive, costs a lot, puts out a lot of power and has a higher latency. They have to put it in quad channel for memory throughput.

With the XeonMP, the last time i checked, they had one main controller and several sub controllers. IF Intel went to XDR and the bandwith that Charlie posted is correct, you can get a lot more bandwith with less latency, power, heat and cost.

I could be completely wrong and i'm waiting for Poncho to tell me so

Look a little closer? Those are 5 Chip sticks, not 8. 5 X 6.4 is 32GB and the 8 chips they're talking about is for Play Station 3. There were other configs talked about with more than just 3.2GHz or 6.4GB. FBDIMMs came down more to Power Draw than costs. Compared to other Server Class Memory it's not that overpriced.

The memory controller or MCH on current XeonDP 771 Boards can be seen as 256Bit or two 128 but the end result is the same.

 

[Donnie27]

Which will still have to be funnelled through a piddly 1333 FSB which is somewhere right around 10GB/s then that has to be shared between cores, so you'll only get about 2.5 GB/s per core...

So ya see it really doesnt matter untill Intel does something about the buss..

Besides your math is faulty... It would be correct if each chip was serial with a DDR signal. But it's not.... It's 16bit chips. at 3.2 Ghz on a shared buss... The buss is prolly DDR. or some derivitive.

soooo 16bits x 3.2 x ddr equals 102.4 GB/s second per dimm.

Speaking of Faulty math, start with yours. I know you LIKE shortchangin' Intel whenever possible but this is silly That's 10.6GB, not 10. That's rounded up similar to PC-2700 that the AthlonXP used for years LOL! 2.65GB per core that will be smartly switch on or off or given smart access to eachother's cache.

Then we don't know if Penryn will ship with 1333 or even an easier for XDR or XDR2 1600MHz FSB. Or if Intel will up the bit width for the FSB. Again, NO ONE KNOWS!

You can't even spin FUD for the Server models that will use multiple FSBs and in the cases of IBM and NEC, multiple North Bridges & MCHs, sheesh!

http://www.rambus.com/us/products/xdr_xdr2/
http://www.channelregister.co.uk/2005/07/07/rambus_xdr_2/
http://www.vr-zone.com/?i=2416&s=1

RAMBUS talked about XDR that could be out by the time 45nm Intel chips ship. These news Items were from July of last year. Are folks suprised? AMD signed a 75 million dollar agreement with RAMBUS as well.

http://www.channelregister.co.uk/2006/01/03/amd_licenses_rambus/

 

[eno-on]

It wont happen as long as intel is not using on die memory controllers. Promise.
It may not happen even after that.
You can quote me.

 

[Dan_D]

It wont happen as long as intel is not using on die memory controllers. Promise.
It may not happen even after that.
You can quote me.

I am pretty sure Intel will never go with an on-die memory controller. Not as long as they can make up the overall performance of their platform another way. At present the Core 2 Duo performance is quite a bit higher than AMD's. Intel has done this without adding an on-die memory controller. So, while this architecture is the mainstream for Intel CPU's and while AMD's architecture is still relatively unchanged from the basic socket 939/AM2 design, Intel has no need to change how things work.

Intel has stated before that the reason they don't have an on-die memory controller is due to the complete lack of flexibility that such a design has.

 

[Donnie27]

I am pretty sure Intel will never go with an on-die memory controller. Not as long as they can make up the overall performance of their platform another way. At present the Core 2 Duo performance is quite a bit higher than AMD's. Intel has done this without adding an on-die memory controller. So, while this architecture is the mainstream for Intel CPU's and while AMD's architecture is still relatively unchanged from the basic socket 939/AM2 design, Intel has no need to change how things work.

Intel has stated before that the reason they don't have an on-die memory controller is due to the complete lack of flexibility that such a design has.

QFT!

 

[eno-on]

I am pretty sure Intel will never go with an on-die memory controller. Not as long as they can make up the overall performance of their platform another way. At present the Core 2 Duo performance is quite a bit higher than AMD's. Intel has done this without adding an on-die memory controller. So, while this architecture is the mainstream for Intel CPU's and while AMD's architecture is still relatively unchanged from the basic socket 939/AM2 design, Intel has no need to change how things work.

Intel has stated before that the reason they don't have an on-die memory controller is due to the complete lack of flexibility that such a design has.

That's true.
They still wont be going rambus.

 

[Donnie27]

That's true.
They still wont be going rambus.

IMHO, Intel will go back to RAMUS but not put all of their eggs into one basket like they did last time. THere will be RAMBUS and DDR-2/3 based stuff to compete for buyer's dollars.

Intel will also move to an Integrated Memory controller when it makes sense for them to do so. Right now, it makes little sense. Expense vs. Performance Gain might determain when they'll make that move. Why bother if they don't need it? Yes there are CSI and other things Intel will do clean up bottlenecks.

 

[eno-on]

IMHO, Intel will go back to RAMUS but not put all of their eggs into one basket like they did last time. THere will be RAMBUS and DDR-2/3 based stuff to compete for buyer's dollars.

Intel will also move to an Integrated Memory controller when it makes sense for them to do so. Right now, it makes little sense. Expense vs. Performance Gain might determain when they'll make that move. Why bother if they don't need it? Yes there are CSI and other things Intel will do clean up bottlenecks.

I have clients that work for intel. They say no Rambus, I asked them.

 

[duby229]

wait, isn't that what i said?

http://www.theinquirer.net/default.aspx?article=18371

Not exactly :d You alluded to a serial memory buss. It's not. It's 16bits. It actually has morebandwidth then yougive it cridit for, and at that clock latencies will be ungodly low. On paper it seems likea kick ass technology. I cant wait to see it in action.

 

[duby229]

Speaking of Faulty math, start with yours. I know you LIKE shortchangin' Intel whenever possible but this is silly That's 10.6GB, not 10. That's rounded up similar to PC-2700 that the AthlonXP used for years LOL! 2.65GB per core that will be smartly switch on or off or given smart access to eachother's cache.

Then we don't know if Penryn will ship with 1333 or even an easier for XDR or XDR2 1600MHz FSB. Or if Intel will up the bit width for the FSB. Again, NO ONE KNOWS!

Although I greatly enjoy watching you grasp at straws, please stop... It's embarrassing.

I did say somewhere right arond 10, did I not? And isnt 10.6 GB/s somewhere right around 10? And it really is a shame that you think it is adequate that Intels quad core has a comparable worst case bandwidth that is similar to AMD's AXP technology... And on the topic of FSB.... I hope your joking. You and I both know Intel is bustin some major ass on CSI. It may well have some Rambus technology built in, but it wont be a FSB.

Your runnin out of straws.

 

[Donnie27]

Although I greatly enjoy watching you grasp at straws, please stop... It's embarrassing.

I did say somewhere right arond 10, did I not? And isnt 10.6 GB/s somewhere right around 10? And it really is a shame that you think it is adequate that Intels quad core has a comparable worst case bandwidth that is similar to AMD's AXP technology... And on the topic of FSB.... I hope your joking. You and I both know Intel is bustin some major ass on CSI. It may well have some Rambus technology built in, but it wont be a FSB.

Your runnin out of straws.

What's really embarrasing are your constant weak attemps at FUD LOL!

Listen, I said each core would have the same bandwidth a PC-2700 enabled AthlonXP. But only you would you figure one AthlonXP while we're talking about 4, get it? Yes, it has everything to do with FSB but some of these systems with have 2, 4 and you 8 FSBs

Reaching for straws? Hell, you're throwing a whole box in my Lap.

You know what I enjoy? My Conroe system that according to you, I wouldn't have until Nov, hehehe.

10.6 is not the same as 10=P
Count the chips on that stick of memory?

Most apps or even Multitasking will never saturate the FSB on Kentsfield or Cloverton.

http://www.xtremesystems.org/forums/showthread.php?t=115384
http://www.xtremesystems.org/forums/showthread.php?t=114282
http://www.tomshardware.com/2006/09/10/four_cores_on_the_rampage/

So yeah, show us this bottleneck? Yes, I know CSI is going to kick ass but there will be instances where it will make NO difference. Intel has advantages in that their processors will work smarter! They will not need as much Brute Force (bandwidth) as AMD's.

Again, look up and read about IBM's Summit and NEC's version it as well?

 

[D4hPr0]

And isnt 10.6 GB/s somewhere right around 10?

Its actually closer to 11 not 10 and most of us learned that in grammar school.

 

[duby229]

Its actually closer to 11 not 10 and most of us learned that in grammar school.

Semantics. 10 11 dont really matter when we are talkin about memory banswidth of 100GB/s second. What good is 10-11GB/s in comparison. With that kind of bottleneck that severe. It really doesnt matter does it?

 

[Donnie27]

Semantics. 10 11 dont really matter when we are talkin about memory banswidth of 100GB/s second. What good is 10-11GB/s in comparison. With that kind of bottleneck that severe. It really doesnt matter does it?

So, if the bottleneck is so bad, why is AMD still getting its ass kicked? Again, there were 5 and NOT 8 chips on those sticks and that doesn't equal 100GB of bandwidth.

 

[eno-on]

So, if the bottleneck is so bad, why is AMD still getting its ass kicked? Again, there were 5 and NOT 8 chips on those sticks and that doesn't equal 100GB of bandwidth.

Its bad when you start looking at 8 way or more servers.

 

[duby229]

So, if the bottleneck is so bad, why is AMD still getting its ass kicked? Again, there were 5 and NOT 8 chips on those sticks and that doesn't equal 100GB of bandwidth.

Where did I say 8 chips on the DIMM? Here is what I said.....

soooo 16bits x 3.2 x ddr equals 102.4 GB/s second per dimm.

Where did I mention 8 chips on a DIMM? I just simply pointed out that it will be 16 bits running at 3.2ghz, prolly DDR or some derivitive which added up equals to about 102GB/s per DIMM.....

Maybe you should learn to read? Oh wait,, hehe I forgot that has been suggested before and you still havent figured out what it means Never mind.... I can also remember asking you to look into the difference between architecture and platform, and clearly you havent figured out what that means either.

 

[Donnie27]

Where did I say 8 chips on the DIMM? Here is what I said.....

Where did I mention 8 chips on a DIMM? I just simply pointed out that it will be 16 bits running at 3.2ghz, prolly DDR or some derivitive which added up equals to about 102GB/s per DIMM.....

Maybe you should learn to read? Oh wait,, hehe I forgot that has been suggested before and you still havent figured out what it means Never mind.... I can also remember asking you to look into the difference between architecture and platform, and clearly you havent figured out what that means either.

Me learn to read? Why would I expect anything less from someone who doesn't know how a frackin’ MCH works ? Link us to something showing this Bottleneck you keep complaining about as Intel still keeps kicking AMD's ass? Oh I can't read it, that's right LOL!

Again, give me a link or you're just doing your normal blowing it out of your ass. It's not only that you have problems reading and writing but counting as well. There's no "prolly" anything, there are hard numbers and if you could count you'd know that LOL! Again, if you can't read the links, have someone else read them and explain it to ya'

2*3.2 GHz = 6.4 GB/sec (per chip) * 8 (8 chips/module) = 51.2 GB/sec

and if it does dual channel, it would be 102.4 GB/sec

2-byte wide, 3.2 GHz XDR DRAM component provides 6.4 GB/sec of peak bandwidth.

The other link showed each stick having 5 Chips and NOT 8. SO, you're either burying your head in the sand or have it up your ass!

 

[eno-on]

Doesn't matter, not gonna happen anyway.

 

[Donnie27]

Its bad when you start looking at 8 way or more servers.

That's possible but it depends more on the Platform.

 

[Donnie27]

Doesn't matter, not gonna happen anyway.

I'll believe it when it doesn't happen.