Intel to Demonstrate PowerVia on E-Core Processor Built with Intel 4 Node

erek

erek

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Interesting, still not sold on these efficiency cores

“Not only does PowerVia provide better frequency and reduced IR drop, but thermal management is a significant benefit as well. As logic scaling continues, more transistors are packed in a smaller space, increasing the thermal density. PowerVias should allow that to be a smaller problem and help heat escape more efficiently. Even though PowerVia is scheduled for the Intel 20A node, the company implemented it for Intel 4 node to learn and present how it works and how it is implemented to Intel Foundry Service (IFS) customers.”

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Source: https://www.techpowerup.com/308234/...a-on-e-core-processor-built-with-intel-4-node
 
erek said:
Interesting, still not sold on these efficiency cores

“Not only does PowerVia provide better frequency and reduced IR drop, but thermal management is a significant benefit as well. As logic scaling continues, more transistors are packed in a smaller space, increasing the thermal density. PowerVias should allow that to be a smaller problem and help heat escape more efficiently. Even though PowerVia is scheduled for the Intel 20A node, the company implemented it for Intel 4 node to learn and present how it works and how it is implemented to Intel Foundry Service (IFS) customers.”

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Source: https://www.techpowerup.com/308234/...a-on-e-core-processor-built-with-intel-4-node
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I like them and they are possibly Intel's best bet against ARM-based servers, if they could integrate these into their upcoming E-core-based Xeon lineup that could be a big deal.
For most data centers the CPU does not remain pinned and they are mostly moving a crapload of data and small things, core counts not individual core strengths are king there and it is what makes ARM so very attractive right now.
ARM does not use any sort of hyper-threading for their cores, which for heavily transactional servers, such as web hosts or payment gateways that is a very big deal and the more individual cores you have there the better.
The core density that a 4 socket E-core based Xeon would put Intel in a space where it could directly compete with ARM in the data center and telecom space and that is even more of a threat than AMD is, because Intel and AMD can trade back and forth for decades, but once they lose a server stack to ARM it's lost to both of them.
 
serpretetsky said:
I think this news is more about PowerVias then it is E-cores. E-cores are just the testing ground. Will be interesting to see the results.
https://www.anandtech.com/show/1682...-3nm-20a-18a-packaging-foundry-emib-foveros/3
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It’s a good one though because finding better ways to move heat out of dense systems is big business. Could save a lot on energy bills. The sooner they can get this deployed the better because Intel needs any leg up it can get right now.
 
It's a scheduling nightmare, but not unthinkable in terms of what might actually be used effectively.
 
What the heck is IR drop? Is this some dopey way of saying "voltage"?

The original site has only a 1-paragraph summary of the talk so the term isn't defined.
 
1_rick said:
What the heck is IR drop? Is this some dopey way of saying "voltage"?
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Heh, yeah. Ohmic loss. Not sure entirely sure why. Maybe to emphasize it's ohmic nature, as oppose to voltage drop during transients due to inductance?

edit: I suppose not even just transients, but also to emphasize that it's not voltage drop to due to non ohmic devices (transistors, diodes, etc). Basically to emphasize that the problem is WIRES.
 
erek said:
Interesting, still not sold on these efficiency cores

“Not only does PowerVia provide better frequency and reduced IR drop, but thermal management is a significant benefit as well. As logic scaling continues, more transistors are packed in a smaller space, increasing the thermal density. PowerVias should allow that to be a smaller problem and help heat escape more efficiently. Even though PowerVia is scheduled for the Intel 20A node, the company implemented it for Intel 4 node to learn and present how it works and how it is implemented to Intel Foundry Service (IFS) customers.”

View attachment 568490
Source: https://www.techpowerup.com/308234/...a-on-e-core-processor-built-with-intel-4-node
Click to expand...
Intel Is All-In on Backside Power Delivery

The company’s PowerVia interconnect tech demonstrated a 6 percent performance gain

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"
You might expect that having to build interconnects on both sides of the silicon would make the cost of the chip shoot up. But early on, Intel saw a reason why that would not be the case, says Sell. The smallest, most tightly packed layer of interconnects, called M0, are also the costliest to produce. They can require more than one pass through chipmaking’s most expensive step, extreme ultraviolet lithography. But with no power interconnects to get in the way, the lines in the M0 layer could be six nanometers further apart than they are today. That may not seem like much, but it means it takes less EUV effort to make them. For the process to be introduced next year and for its successor, “the cost savings we get from not scaling so aggressively more than offsets the additional cost from the backside power-delivery process,” Sell says.
​

Derisking PowerVia​

If the plans for PowerVia were going to work, the technology had to meet certain criteria, most of which have to do with not making things worse: Despite existing in a much thinner layer of silicon, the transistors had to work just as well; the power delivery network had to be just as reliable as those built on the front side of the silicon; the heat generated in the silicon couldn’t get out of hand, despite the transistors being sandwiched between interconnect layers; and the ability to debug ICs and spot design defects can’t be hampered.

It took some doing to meet these criteria. For example, the power-interconnect process had to be tweaked to keep from affecting the transistors. And Intel had to set some design rules to keep thermal issues in line. It also had to come up with new methods to make debugging work.

On top of all that, Intel engineers had to ensure that the PowerVia chips’ yield—the fraction of good chips per wafer—was on target to reach high-volume manufacturing, even though these particular chips will never be sold. The goal here was for the yield of Intel 4 PowerVia chips to match those of Intel 4 chips from 9 months ago. PowerVia chips were always going to lag, because any improvements to Intel 4’s yield would take time to translate to the PowerVia experiments. “We did a bit better than that,” says Sell. PowerVia’s yield curve follows Intel 4’s by only 6 months.

2024 and Beyond​

With the process for PowerVia worked out, the only change Intel will have to make in order to complete its move from Intel 4 to the next node, called 20A, is to the transistor. RibbonFET, Intel’s take on nanosheet, or gate-all-around, transistors, will then slot in to the already established interconnect scheme.

If all goes well, and Sell says all is going well, the 20A process will be making the company’s Arrow Lake CPUs in 2024. The following technology generation, called 18A, is meant for both Intel products and foundry customers.

Success would put Intel ahead of TSMC and Samsung, in offering both nanosheet transistors and backside power. Samsung has already moved to a gate-all-around device, and it’s unclear when it will integrate backside power. TSMC is scheduled to offer gate-all-around devices in 2025, but it won’t be adding backside power delivery until at least 2026."

https://spectrum.ieee.org/backside-power-delivery
 
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