Intel SkyLake inverse hyper threading

[sblantipodi]

Hi, it seems that the new skylake has a new interesting features, inverse hyperthreading.

As far as I understood the new architecture boosts single threaded performance because let the operating system to use multiple virtual threads for a single thread software thread.

It seems very interesting, is there someone who has more info or some benchmark that shows the differences and the improvements?

 

[pxc]

I don't think that necessarily means "reverse hyperthreading".

Intel states that one core can use resources from another core. The easiest thing to do is probably link the caches and/or SIMD units. 470.ibm in SPEC CPU2006 is a floating point test, so doing that along with compiler autovectorization (for parallel SSEx/AVX code) could lead to the massive single thread performance increase in that test compared to Haswell. That throughput increase certainly suggests that one core can use the SIMD unit(s) from one or more other cores.

 

[GotNoRice]

As far as I understood the new architecture boosts single threaded performance because let the operating system to use multiple virtual threads for a single thread software thread.

Well the CPU is already out and has already been benchmarked. Nothing stands out as having given it a great performance boost in this regard. This sounds more like the result of one site releasing a click-bait article and it spreading across the internet like wildfire.

 

[obiwansotti]

It does not.

If it did, intel would have made a stinking big deal about it yesterday.

 

[zaniix]

I thought this was just a rumor so far, did you see something new from Intel about this?

 

[obiwansotti]

I thought this was just a rumor so far, did you see something new from Intel about this?

Intel did their full monty release of skylake info yesterday. IDF is where they would have crowed about this being a huge new jewel in their tech chest. But none of the information released mentioned anything remotely similar to this I think we can chalk this one up as total click-bait, not worth time or thought.

 

[pxc]

Intel did their full monty release of skylake info yesterday. IDF is where they would have crowed about this being a huge new jewel in their tech chest. But none of the information released mentioned anything remotely similar to this I think we can chalk this one up as total click-bait, not worth time or thought.

OP's linked article is based on a pretty good source (but then does the usual wccftech crapification): http://www.heise.de/newsticker/meldung/Skylake-mit-inversem-Hyper-Threading-2779793.html The test results are solid, but Heise is speculating about the cause.

There are different reasons for at least part of the increase, including uarch improvements (L1 data/L2 bandwidth, better reordering, FMA3), but that doesn't really explain over a 2x speedup.

In addition to what I wrote earlier, I wonder if desktop/mobile Skylake actually has AVX-512, but it's not exposed directly. By that I mean certain non-dependent operations that would have been queued for sequential execution could be executed in parallel with regular AVX2.0 operations. AMD had a similar symmetrical layout in Bulldozer modules IIRC.

 

[defaultluser]

Could it be improved prefetch breaking the benchmark?

The incredible improvement in the Core 2 cache controller prefetch broke ScienceMark 2.0:

http://www.anandtech.com/show/2045/5

Those results were atypical of all-around memory performance. Prefetch can only work those kinds of miracles in corner cases

I mean, it wouldn't be the first time Intel's cache prefetch had created inconsistent performance increases. And we know for sure that the Core i3 tends to get a whole lot more speedup in HT situations than the Core i7, mostly due to more available memory bandwidth per-thread. As you add more threads to the benchmark, you get less bandwidth per-thread, so the falloff would be expected.

This article says prefetching has been massively revamped in Skylake:

http://arstechnica.com/information-...skylake-uses-to-go-faster-and-use-less-power/

And massively touching the prefetch for the majority of performance improvements on Skylake would explain why the performance per clock improvement is so inconsistent. Prefetch is the "best guess," and it's not always right.

But I think PXC could also be onto something there. Could those 512-bit wide vector units be available on all processors?

 

[defaultluser]

Also, there's a discussion about this anomaly I just found at Real World Tech.

http://www.realworldtech.com/forum/?threadid=152437&curpostid=152437

General consensus: this test in particular likes bandwidth! It's the wider front-end and better prefetch + DDR4:

470.lbm likes external bandwidth a lot. See the following article for instance:

http://www.ittc.ku.edu/~heechul/papers/memguard-2015-tc.pdf

So I bet this is rather due to higher DDR4 bandwidth and better HW prefetch (that helps a
single core saturate external bandwidth with a single thread something that was not
possible on Haswell [at least it wasn't possible on my 4770K with DDR3-2400]).

The following article is also very interesting to understand 470.lbm sensitivity to
prefetch:

http://www.cc.gatech.edu/~hyesoon/lee_taco12.pdf

The original author of this article is at IDF and refuted his own claims today (german): http://www.heise.de/newsticker/meld...in-wenig-die-Skylake-Architektur-2784862.html

His explanation for the performance discrepancies are the L3 cache and the L2 & L3 fabric where he assumes that due to double-wide lanes cache-misses are handles twice as fast.

 

[pxc]

This article says prefetching has been massively revamped in Skylake:

http://arstechnica.com/information-...skylake-uses-to-go-faster-and-use-less-power/

Yeah, that may be a big part of it. Andreas Stiller at Heise dismisses inverse hyperthreading: http://www.heise.de/newsticker/meld...in-wenig-die-Skylake-Architektur-2784862.html

He mentions the L2 cache bandwidth increases, improvements to the ring bus fabric between L2 and L3, improved prefetch, and TLB improvements. Along with higher DDR4 bandwidth that may explain most of it. I'll add in it's probably also due to compiler improvements since no application benchmarks improved anywhere near as much between Skylake and Haswell.

 

[defaultluser]

Yeah, that may be a big part of it. Andreas Stiller at Heise dismisses inverse hyperthreading: http://www.heise.de/newsticker/meld...in-wenig-die-Skylake-Architektur-2784862.html

He mentions the L2 cache bandwidth increases, improvements to the ring bus fabric between L2 and L3, improved prefetch, and TLB improvements. Along with higher DDR4 bandwidth that may explain most of it. I'll add in it's probably also due to compiler improvements since no application benchmarks improved anywhere near as much between Skylake and Haswell.

Yeah, when I heard the behavior, I thought his guess was crazy. And since IDF was right around the corner, I figured they would reveal a smoking gun that hot if they were actually packing.

There was no gun