Intel Quickpath Interconnect, explain please?

[bigdogchris]

I was looking at the Core i7 technology, to get a better understanding of how it benefits from DDR3, and noticed a while back they removed the FSB (as we know it), which everyone knows already. They now measure the speed in GT/s, rather than a FSB.

As for DDR3, there is anywhere from DDR 1066 to 2000MHZ.

I'm trying to figure how GT/s relates to memory. We all know a 333FSB of a core 2 uses the memory equivalent to 667mhz dd2 for 1:1.

This is where I get stuck. Is 2000mhz DDR3, 2GT/s? Or since it's double data rate, actually 4GT/s? I've also thought I read something where ddr3 is actually 4x cycles per clock, so 1066ddr3 is actually 4264 equivalent, thus 4.2GT/s, meaning you would need around 1333DDR3 to be slightly faster than the 4.6GT/S of the corei7.

How far off am I? I think i'm close at figuring this out.

 

[Zero82z]

DDR3 is not 4 cycles per clock. From a practical perspective, it's basically just faster DDR memory. The 1333, 1600, 2000, etc. speeds are also already pre-doubled, just like DDR and DDR 2 ratings (ie: DDR-400 = 200MHz, DDR2-800 = 400MHz, etc.).

As for Quickpath, it's basically just a faster direct interface between the CPU and the RAM. The memory controller is integrated into the die which allows the CPU to make use of a direct connection between itself and the RAM instead of having to go through the FSB to the memory controller embedded into the northbridges of old. This has no effect on the speed of DDR3 memory (only the bandwidth), so treat the ratings the same as you would for a Core 2 system using DDR3.

 

[Atech]

A must read:
http://www.realworldtech.com/page.cfm?ArticleID=RWT082807020032&p=1

 

[Scali2]

I think a few basic pieces of info might help you on your way:
1) DDR, DDR2 and DDR3 have the same bandwidth at the same speed (Biggest win for DDR3 is lower voltage, and potentially higher clockspeeds).
2) The fastest Nehalem processors will use 3 memory channels as opposed to 2 on Core2.
3) According to the Realworld article, "Initial CSI implementations in Intel’s 65nm and 45nm high performance CMOS processes target 4.8-6.4GT/s operation, thus providing 12-16GB/s of bandwidth in each direction and 24-32GB/s for each link".

So roughly, to max out the 16 GB/s bus in one direction, you'd have to have memory modules capable of 16/3 = 5.3 GB/s.
I believe the first generation only supports DDR3-800 and DDR3-1066 anyway (officially). I suppose that already should be fine, with 3 channels.

 

[savantu]

You're confusing QPI with the IMC ; QPI has no relation whatsoever to the RAM.

QPI connects CPUs to other devices ( other CPUs or I/O devices ).

GT per second , means just that , gigatransfers per second.Since QPI is 20 bit wide ( 16 data , 4 for RAS ) a transfer is 2 bytes of data , each way.As a result 4.8GTs equals 19.2GBs and 6.4GTs offers 25.6GBs per QPI link.