Intel Engineer Posts Cache-Aware Load Balancing For Linux - May Be Very Useful For AMD

[erek]

“Intel engineer Peter Zijlstra posted the "request for comments" (RFC) patch series today for introducing cache-aware load balancing. As he explained, the code has been in the works for a while albeit only now making it to the mailing list. Peter wrote:”

"One of the many things on the eternal todo list has been finishing the below hackery.

It is an attempt at modelling cache affinity -- and while the patch really only targets LLC, it could very well be extended to also apply to clusters (L2). Specifically any case of multiple cache domains inside a node.

Anyway, I wrote this about a year ago, and I mentioned this at the recent OSPM conf where Gautham and Prateek expressed interest in playing with this code.

So here goes, very rough and largely unproven code ahead

It applies to current tip/master, but I know it will fail the __percpu validation that sits in -next, although that shouldn't be terribly hard to fix up.

As is, it only computes a CPU inside the LLC that has the highest recent runtime, this CPU is then used in the wake-up path to steer towards this LLC and in task_hot() to limit migrations away from it.

More elaborate things could be done, notably there is an XXX in there somewhere about finding the best LLC inside a NODE (interaction with NUMA_BALANCING)."

Source: https://www.phoronix.com/news/Linux-Cache-Aware-Load-Balance

 

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[erek]

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“Intel Updates Cache Aware Scheduling For Linux With Better NUMA Balancing​

Written by Michael Larabel in Intel on 5 December 2025 at 09:38 AM EST. 10 Comments

Intel engineer Tim Chen has sent out a second version of the proposed Cache Aware Scheduling patches for the Linux kernel to enhance the CPU performance of modern processors sporting multiple cache domains.

Cache Aware Scheduling aims to better Linux performance on modern CPUs by co-locating tasks sharing data to the same cache domain to enhance the cache locality and reducing cache misses and cache bouncing.

From their v2 patch message of the Cache Aware Scheduling benefits:

"[TL;DR]

Sappire Rapids:
hackbench shows significant improvement when the number of different active threads is below the capacity of a LLC. schbench shows overall wakeup latency improvement. ChaCha20-xiangshan shows good throughput improvement.

Genoa:
ChaCha20-xiangshan shows huge throughput improvement. No obvious difference is observed in hackbench/schbench /netperf/stream/stress-ng. Phoronix has tested v1 and shows good improvements in 33 cases."

Indeed some benchmarks I ran back in October on AMD EPYC Turin with the prior Cache Aware Scheduling patches were showing some very nice performance benefits. I'll work on testing the v2 patches on some additional hardware as time allows.

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As for the v2 patches, there is improved NUMA balancing and other changes:

"1. Align NUMA balancing and cache affinity by prioritizing NUMA balancing when their decisions differ.
2. Dynamically resize per-LLC statistics structures based on the LLC size.
3. Switch to a contiguous LLC-ID space so these IDs can be used directly as array indices for LLC statistics.
4. Add clarification comments.
5. Add 3 debug patches (not meant for merging).
6. Other changes to address feedbacks from review of v1 patch set."

Those interested can find the v2 patches on the LKML for undergoing the latest round of code review and testing. Hopefully this Cache Aware Scheduling support manages to make it into the mainline Linux kernel in 2026.”

Source: https://www.phoronix.com/forums/for...heduling-for-linux-with-better-numa-balancing

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