Intel Diamond Rapids

[erek]

“Coherence data also moves on to the die. Intel replaces DRAM-resident directory state with an on-die snoop filter, which preserves full ECC protection by removing directory storage from memory and, in turn, lowers latency and cuts coherence traffic.

Hot Chips 2026 Intel Diamond Rapids Slide 19 Data
That performance with 256 cores, 1.28 GB of cache, 1.6 TB/s of memory bandwidth, and 128 lanes of high-bandwidth, low-latency I/O. Matrix multiplication acceleration rides on AMX and AVX 10.2 with expanded vector instruction support.

Hot Chips 2026 Intel Diamond Rapids Slide 20 High-performance
Intel closes the session with the full Diamond Rapids summary. This wrap-up folds the modular compute building blocks, unified memory fabric, 18A-P process technology, and the security and acceleration engines into a single architectural picture.

Hot Chips 2026 Intel Diamond Rapids Slide 21 Performance Efficiency Acceleration Scalability Security
That covers the Diamond Rapids architecture as presented in today’s talk.

Final Words​

Diamond Rapids is Intel’s answer to the high-core-count, high-memory-bandwidth server lane as the platform heads toward 2027 against AMD’s EPYC push. It seems like Intel updated its roadmap recently to match AMD’s 256 cores since AMD’s 256-core design is an all-P-core design (albeit with 512 threads). Moving coherency on-die, stacking with 3D, and stepping up to the 18A-P process all help close the efficiency gap with the competition. Still, it seems like Diamond Rapids is going to be a second-half-of-2027 part, so we have some time to go.”

Source: https://www.servethehome.com/intel-diamond-rapids-the-2027-intel-xeon-at-hot-chips-2026/

 

[Lakados]

“Coherence data also moves on to the die. Intel replaces DRAM-resident directory state with an on-die snoop filter, which preserves full ECC protection by removing directory storage from memory and, in turn, lowers latency and cuts coherence traffic.

Hot Chips 2026 Intel Diamond Rapids Slide 19 Data
That performance with 256 cores, 1.28 GB of cache, 1.6 TB/s of memory bandwidth, and 128 lanes of high-bandwidth, low-latency I/O. Matrix multiplication acceleration rides on AMX and AVX 10.2 with expanded vector instruction support.

Hot Chips 2026 Intel Diamond Rapids Slide 20 High-performance
Intel closes the session with the full Diamond Rapids summary. This wrap-up folds the modular compute building blocks, unified memory fabric, 18A-P process technology, and the security and acceleration engines into a single architectural picture.

Hot Chips 2026 Intel Diamond Rapids Slide 21 Performance Efficiency Acceleration Scalability Security
That covers the Diamond Rapids architecture as presented in today’s talk.

Final Words​

Diamond Rapids is Intel’s answer to the high-core-count, high-memory-bandwidth server lane as the platform heads toward 2027 against AMD’s EPYC push. It seems like Intel updated its roadmap recently to match AMD’s 256 cores since AMD’s 256-core design is an all-P-core design (albeit with 512 threads). Moving coherency on-die, stacking with 3D, and stepping up to the 18A-P process all help close the efficiency gap with the competition. Still, it seems like Diamond Rapids is going to be a second-half-of-2027 part, so we have some time to go.”

Source: https://www.servethehome.com/intel-diamond-rapids-the-2027-intel-xeon-at-hot-chips-2026/

I like that Intel is doing cool shit.

 

[erek]

I like that Intel is doing cool shit.

“Intel presented Diamond Rapids at Hot Chips, so here is the full slide deck breakdown of the 2027 Xeon. Intel moves to a fan-out fabric: compute building blocks made of four 16 core chiplets stacked on a base tile holding the last level cache, all wired into two central fabric hubs. The peak configuration hits 256 P cores, 1.28 GB of last level cache, 16 channels of DDR5 and 128 lanes of PCIe Gen 6, built on 18AP, Intel 3 and 3T with Foveros Direct and UCIe. I also work out the die to die bandwidth Intel left off the slides.”


View: https://youtu.be/4oT7OEkAwnY?is=MZ7C6wpuuyZ8zzmM