Imec Develops New CXL Buffer Memory That Could Surpass DRAM Bit Density

[erek]

"As a first step towards real implementations, imec demonstrated memory operation of the CCD with IGZO on a 2D proof-of-concept. The planar CCD structure of this 2D proof-of-concept consists of an input stage, 142 stages (each consisting of four phase gates) which can each store one bit, and a two-transistor-based read-out stage. The CCD register is written by injecting charges through the input stage and sequentially transferring them through all 142 stages by switching the voltages of the phase gates. The CCD offers more than 200s retention, an endurance of >1010 cycles without degradation, and a charge transfer speed exceeding 6 MHz. Multilevel storage capability of the CCD register was also demonstrated, contributing to a higher bit density. Being widely adopted in the image sensor market, the charge-based CCD technology is well-known, reliable, and can operate at low voltages - benefiting power consumption."

Maarten Rosmeulen, Program Director Storage Memory at imec: "The real value of the proposed buffer memory lies in its ability to be integrated into 3D NAND fashion, with IGZO-based CCD registers integrated into vertically aligned plugs - a concept that we now propose for the first time. From what is possible with NAND Flash today (i.e., the capability of processing 230 layers), we estimate that our 3D buffer memory can already provide five times more bit density than what (2D) DRAM is expected to offer in 2030. We are currently investigating real 3D implementations with limited number of word lines."

Source: https://www.techpowerup.com/329779/...er-memory-that-could-surpass-dram-bit-density

 

[1_rick]

DRAM that can only be written 1000 times? Surely that's not what it meant. A confusing snippet. Oh, it's not DRAM, so I'm not sure why they're comparing the relative size.

 

[Lakados]

DRAM that can only be written 1000 times? Surely that's not what it meant. A confusing snippet. Oh, it's not DRAM, so I'm not sure why they're comparing the relative size.

CXL functions as a buffer between the CPU and RAM in large data centers
https://www.micron.com/content/dam/...expansion-a-close-look-on-actual-platform.pdf
RAMBUS has a good explanation of it as well
https://www.rambus.com/blogs/compute-express-link


Basically, it lets you synchronize RAM across entire hardware stacks to better feed accelerators and whatnot, so if a job spills over server A it can be fed into server B and so on, it lets you run larger jobs overall and helps to remove situations where your jobs fail because they hit a memory wall or a deadlock. So as it functions as an interface to DRAM comparing it to DRAM is somewhat appropriate.

It should be worth noting here degradation doesn't refer to the cell physically breaking down, but the data contained within that cell becoming corrupted. So they are saying the data is good for 200 seconds or 1010 reads, whichever comes first, after which the charge will begin to decay corrupting the stored value.

 

[1_rick]

It should be worth noting here degradation doesn't refer to the cell physically breaking down, but the data contained within that cell becoming corrupted. So they are saying the data is good for 200 seconds or 1010 reads, whichever comes first, after which the charge will begin to decay corrupting the stored value.

Ah, I did not get that from the article at all, but it makes sense.