Hypertransport Questions

[ricetek]

Can someone explain Hypertransport on A64's how ram and fsb relate to HT. Cause nforce3 mobos use ddr400 ram.

 

[Elios]

here

  _____          ______
  | PCI|         | AGP |        _________                        __________
  |____|         |_____|       |         |                       |         |
     |                 |______ | N.bridge|___HyperTransport link_|   CPU   |
     |_________________________|         |                       |         |
                               |_________|                       |_________|
                                               _______________         |
                                               |__SYS. RAM____|________|

ok heres how this all work you mem runs a DDR400 or 200Mhz double clocked
the HTT bus run off a mulitplyer like the cpu take my setup for ex.
CPU speed is based on a 10x muti soo 10xmem clock or 200 at stock = 2Ghz
now the HTT bus gets its clock from the mem too soo it has a 4x muti for the stock 800Mhz so HTT = 8x200 but the HTT is also double clocked after the muti soo
(2xHTT) = 8x200

 

[burningrave101]

I think you mean system clock instead of memory clock. The memory clock runs at a ratio of the system clock. Its the system clock that the CPU and HTT bus derive their clock frequencies from.

The HTT bus is double data rate so it can transfer data in both directions at the same time. This is why you see 1600Mhz and 2000Mhz being advertised on motherboards and such things because 2x800Mhz HTT = 1600Mhz and 2x1Ghz HTT = 2Ghz throughput.

 

[MrSmegzabush]

What chips run 1ghz HTT?

 

[NEVERLIFT]

DDR aka double data rate means it can read and write to the memory at the same time... no waiting.

 

[burningrave101]

I think this article will explain all your HyperTransport questions.

http://www.short-media.com/review.php?r=206

This highway or BUS is an internal connection. On the motherboard level, the HyperTransport bus connects all parts of the motherboard, such as the PCI slots, AGP slots and USB ports to the CPU and memory and also provides the connection between the CPU and memory itself (although it is a bit more complicated than this. The Hammer processors actually connect to memory directly but use HyperTransport to communicate with the memory of other processors in a multiprocessor configuration since HyperTransport is also a coherent bus). At present, the internal PCI bus used in current systems is a rather small road, limited to a small amount of traffic, supporting a maximum data rate of 133 Megabytes per second. This may seem like a lot of data, but when compared to the memory and CPU shoving data around at 2.1 Gigabytes per second and video cards nearing 20 Gigabytes per second, the internal bus is very limiting.

DDR means there is an Upstream and Downstream path on the HyperTransport bus. It can for example transfer 800Mhz upstream and 800Mhz downstream which totals 1600Mhz effective.