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Ok, I have a rather complicated issue with PCIE lanes.
For reference, the motherboard in question is ASRock Z170 Fatal1ty Gaming K6.
ASRock > Fatal1ty Z170 Gaming K6
I can be wrong so feel free to correct me.
I read that Z170 motherboards have a total of 42 lanes, 16 of which are directly connected to the CPU, and the remaining 26 are connected to the PCH (chipset).
However, of the remaining 26 PCIE lanes, 6 are exclusively connected to USB 3.0 ports, and up to additional 4 lanes may be reserved for the same purpose, so that leaves the chipset with really 20 PCIE lanes, had the manufacturer decided to pack in as many connections to the board as possible, much like the K6 I would say, with USB 3.1 type A and C, Thunderbolt, a third PCIE x 16 slot, 3 PCIE x 1 slots, and a M.2 running at PCIE x 4. (almost as many as Asus Z170 Pro Gaming, one I have been comparing to.)
On the K6, as aforementioned, there are 3 PCIE x 16 slots, and the first 2 I think are connected to the CPU because they run either X 16 (only one used) or X 8/X 8 (both used), and the last one I think is connected to the chipset, because according to the specs, if all three are used, they run X8 / X8 / X4 (so not sharing the CPU-connected PCIE lanes I think.)
Assuming I have both CPU-connected PCIE slots taken, (one for GTX card and the other for PCIE X 4 SSD), had I wanted to add an additional SSD, is it best to put it in the third PCIE slot, M.2 X 4 slot, or SATA? (best in terms of less resource sharing with the first 2 CPU-connected PCIE devices. My understanding is, somehow, the lanes, whether connected to the CPU or the chipset, all share bandwidth on the board.)
I have read posts where the M.2 is disabled because too many connections are taken, for example.
Or am I wrong, that the first two CPU-connected PCIE only share bandwidth among each other, and the third PCIE shares bandwidth with all remaining ports on the board (including those 3 PCIE X 1 slots, but not with the first two PCIE X 16 slots directly linked to the processor?)
If that's the case, does that mean the first two PCIE slots have dedicated bandwidth, which only those two can share, and even if all remaining 26 lanes are all taken (42-16=26), there is no performance penalty on those two PCIE slots? (but there is performance penalty for those sharing those 26 lanes, including the third PCIE slot, which is why the M.2 port may be disabled if too many SATA ports are used, for example.)
Thank you.
For reference, the motherboard in question is ASRock Z170 Fatal1ty Gaming K6.
ASRock > Fatal1ty Z170 Gaming K6
I can be wrong so feel free to correct me.
I read that Z170 motherboards have a total of 42 lanes, 16 of which are directly connected to the CPU, and the remaining 26 are connected to the PCH (chipset).
However, of the remaining 26 PCIE lanes, 6 are exclusively connected to USB 3.0 ports, and up to additional 4 lanes may be reserved for the same purpose, so that leaves the chipset with really 20 PCIE lanes, had the manufacturer decided to pack in as many connections to the board as possible, much like the K6 I would say, with USB 3.1 type A and C, Thunderbolt, a third PCIE x 16 slot, 3 PCIE x 1 slots, and a M.2 running at PCIE x 4. (almost as many as Asus Z170 Pro Gaming, one I have been comparing to.)
On the K6, as aforementioned, there are 3 PCIE x 16 slots, and the first 2 I think are connected to the CPU because they run either X 16 (only one used) or X 8/X 8 (both used), and the last one I think is connected to the chipset, because according to the specs, if all three are used, they run X8 / X8 / X4 (so not sharing the CPU-connected PCIE lanes I think.)
Assuming I have both CPU-connected PCIE slots taken, (one for GTX card and the other for PCIE X 4 SSD), had I wanted to add an additional SSD, is it best to put it in the third PCIE slot, M.2 X 4 slot, or SATA? (best in terms of less resource sharing with the first 2 CPU-connected PCIE devices. My understanding is, somehow, the lanes, whether connected to the CPU or the chipset, all share bandwidth on the board.)
I have read posts where the M.2 is disabled because too many connections are taken, for example.
Or am I wrong, that the first two CPU-connected PCIE only share bandwidth among each other, and the third PCIE shares bandwidth with all remaining ports on the board (including those 3 PCIE X 1 slots, but not with the first two PCIE X 16 slots directly linked to the processor?)
If that's the case, does that mean the first two PCIE slots have dedicated bandwidth, which only those two can share, and even if all remaining 26 lanes are all taken (42-16=26), there is no performance penalty on those two PCIE slots? (but there is performance penalty for those sharing those 26 lanes, including the third PCIE slot, which is why the M.2 port may be disabled if too many SATA ports are used, for example.)
Thank you.