no no you guys have this all wrong. Saying that a cpu is "3-issue" or "4-issue" does not mean that it does that many instructions per clock. IPC varies widly with architecture, from maybe 4 on ineffecient chips to maybe 9 on high effeciency chips (just guesses here, but should be rough ballpark)
What you're thinking of has to do with how many x86 ops can be issued/retired per clock cycle. Most modern cpu's up to conroe have been 3-issue, meaning it can issue/retire 3 ops per clock cycle. Netburst was a bit odd in this regard...it could issue 6 per 2 clock cycles, so it could possibly issue 4 ops in one clock but the next clock was limited to 2 ops.
Conroe is now a 4-issue. It also has some significant improvements in how many SSE operations can be dispatched per clock, which also contributes to the insane performance level it achieves.
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