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High frequency CPU the only opton for single threaded?
- Thread starter Bluelude1
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dragonstongue
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IPC matters as much, cache can help the cores be fed properly, and these days the memory controller can have an impact as well. To keep it on a simple train. If you have an older chip say a Pentium 4 running at a very high frequency vs a more modern one running at more modest frequencies the will get very near the same absolute performance as the modern ones are built to get the most out of every tick of the clock.
This can also be seen with something like the new FX chips which were built around getting a very high speed. While they can hit crazy speeds, they also are not built for efficiency at that speed really and do suffer latency issues due to being built to try and hit very high speeds.
instructions per clock matters as much if not more then just raw frequency, as its the IPC that allows that frequency to "work"
Put another way, a very high IPC and efficient chip that does not have to dump its pipeline very often would and is far better then a chip running at a very high frequency but loose IPC/Power/Heat and has the pipeline get thrashed.
I think IBM has the highest frequency, highest IPC capable, highest core count chips out there, but they are way beyond affordable.
This can also be seen with something like the new FX chips which were built around getting a very high speed. While they can hit crazy speeds, they also are not built for efficiency at that speed really and do suffer latency issues due to being built to try and hit very high speeds.
instructions per clock matters as much if not more then just raw frequency, as its the IPC that allows that frequency to "work"
Put another way, a very high IPC and efficient chip that does not have to dump its pipeline very often would and is far better then a chip running at a very high frequency but loose IPC/Power/Heat and has the pipeline get thrashed.
I think IBM has the highest frequency, highest IPC capable, highest core count chips out there, but they are way beyond affordable.
brutalizer
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I have explained some of this in a discussion on the new coming IBM POWER8 cpu. Here I talk about cache, high Hz, and performance:
http://hardforum.com/showpost.php?p=1040311832&postcount=30
http://hardforum.com/showpost.php?p=1040311832&postcount=30
dragonstongue
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There is the side as well though that high frequency or at least extreme speed interconnects between memory and the cpu and inner core communications i.e between the cores themselves help immensely, IBM and HP both are working on and have prototype cpu that use optical connects to speed this data as fast as possible, so as you put and this is very true at this point because cpu by and large rely on specific code at specific times during a cycle cache misses are a huge performance loss (also why some are working on code that does not directly rely on sequential data in an organized fashion)
The optical side of things at least what many are trying is to try and mitigate that ram is so much slower by speeding the time it talks back to the main cpu and for the main cpu that as you put cache has very strict limits will allow the cache to be used at extreme speeds and with the cores with modern instructions snooping, pre-fetch, allocation markers etc will help mitigate the losses.
Kind of funny though that as you put the Niagra cpu allows cores to stop working on the thread that misses and allows another to work on it, this is what for example AMD is working on allowing their cpu to do in a round-about way by putting markers in the operations to make sure specific run times are ear marked for the cpu/gpu to work on in the memory side.
The other thing is there is many types of memory that various makers are trying to push forth that dwarf the speed, power etc of current memory types though most of this is not small enough to be used in the core itself, but via optical connects it could be a massive amount of memory that can be used directly as cache at very near the same speed modern cpu run at, interesting times.
So either way, the connection type, the way the chips are built, raw frequency all matter, but as I put and have read on IPC and as Brutalizer alludes to, the "quality" of those IPC in regards to misses and stalls matters far far more, even for client side use. They can make chips operate in the THz range however they do not have the current tech to allow it to be used very well in anything but the lab.
Speed is groovy, precision matters more. This is why just as a base example years ago Athlon was running over P4 unless it was clocked extremely high, Athlon was just more intelligent at keeping a shorter pipe at a decent speed, where P4 was made to clock very high via a much deeper pipeline and as such its efficiency was just quite terrible as it had far to many pipeline misses/stalls and would waste time cleaning this out, Athlon did as well as does any modern chip but there is that benefit (currently) it was not running at such extreme speeds that it could not almost fix the stalls on the fly.
I suppose server side this comes into play massively as stalls and misses could literally cause huge problems that could be very very costly in many ways.
The optical side of things at least what many are trying is to try and mitigate that ram is so much slower by speeding the time it talks back to the main cpu and for the main cpu that as you put cache has very strict limits will allow the cache to be used at extreme speeds and with the cores with modern instructions snooping, pre-fetch, allocation markers etc will help mitigate the losses.
Kind of funny though that as you put the Niagra cpu allows cores to stop working on the thread that misses and allows another to work on it, this is what for example AMD is working on allowing their cpu to do in a round-about way by putting markers in the operations to make sure specific run times are ear marked for the cpu/gpu to work on in the memory side.
The other thing is there is many types of memory that various makers are trying to push forth that dwarf the speed, power etc of current memory types though most of this is not small enough to be used in the core itself, but via optical connects it could be a massive amount of memory that can be used directly as cache at very near the same speed modern cpu run at, interesting times.
So either way, the connection type, the way the chips are built, raw frequency all matter, but as I put and have read on IPC and as Brutalizer alludes to, the "quality" of those IPC in regards to misses and stalls matters far far more, even for client side use. They can make chips operate in the THz range however they do not have the current tech to allow it to be used very well in anything but the lab.
Speed is groovy, precision matters more. This is why just as a base example years ago Athlon was running over P4 unless it was clocked extremely high, Athlon was just more intelligent at keeping a shorter pipe at a decent speed, where P4 was made to clock very high via a much deeper pipeline and as such its efficiency was just quite terrible as it had far to many pipeline misses/stalls and would waste time cleaning this out, Athlon did as well as does any modern chip but there is that benefit (currently) it was not running at such extreme speeds that it could not almost fix the stalls on the fly.
I suppose server side this comes into play massively as stalls and misses could literally cause huge problems that could be very very costly in many ways.