Help needed from analog gurus!!!

[joecool234]

I currently have a mixed digital/analog circuit board that requires about 40 decoupling points. Each point has a 10uF tantalum in parallel with a .1uF ceramic cap. Unfortunately, I did not notice that the caps I soldered on had a voltage rating of only 16V. When I powered the board up with 18V, several caps just flat at blew up. Those were simply removed. Now that I am running the board at 15V, everything should be fine...however, analog settling time is just unacceptable. It's on the order of 2-3 times worse than my simulator. So....I have the following questions:

1) Can blown decoupling caps cause adverse settling times?
2) Is it OK to run a 16V cap at 15V?
3) Does decoupling capacitance affect settling times of analog chips?

I;m about to replace every 10uF cap with new ones and continue to run it at 15V. Hoepfully this can correct the problem. But if not, any additional info would be greatly appreciated.

 

[gee]

What kind of analog chips are we talking about? Describe your circuit in more detail.

Also, I don't think you need so many tantalums spread around the board... and running 16V tantalums at 15V isn't necessarily good for them, i'd replace them with an equivalently sized 25V part if you can find one.

 

[Mohonri]

the rating of the capacitors is their maximum rating, above which they're likely to do nasty things. I would also be hesitant about running them so close to their maximum. I would run the board at whatever the original voltage was.

 

[RancidWAnnaRIot]

1) get caps with hire break down voltages... I personally get stuff that is 50% more than what i need.. so if my highest voltage is going to be, say 15V, then i would get a cap with a minimum of 22.5V break down

2) I'm not sure what kind of circuit you're talking about (as others have stated give us more details about the circuit..).. but in general more capcitance slows down reaction time...

 

[joecool234]

Ok...it would take me a year and a day to explain this circuit in detail (and plus I would be violating my NDA). So after I posted this, I went ahead and removed all the tantalums and added new 16V caps to the digital rails. I left the pads for the analog chips open, but they still have .1uF caps at least.

One thing I noticed immediately...ringing was reduced by orders of magnitude. What I thought was a settling time issue was actually relatively low frequency ringing (<10KHz). So the analog stage settles much quicker now.

FYI, the analog stage consists of an INA with a gain of 100...followed by an opamp in inverting configuration with a gain of 20. This then goes into an ADC driver opamp whcih also functions as a 10KHz filter.

As for those tants...I would replace them with a higher voltage rating, but they are SMT parts and we don;t have stock on replacements. I might check and see if we have 1uF, but its unlikely. I might just keep the board as is.

Thanks for your help guys.

 

[Aristarchus]

40x 10uF SMT tantalums per board? Dude, you gotta be spending a fortune on caps... Do consider also that tantalums aren't necesarily the be all & end all of capacitors. For decoupling purposes especially, it's more a question of having a set of caps whose self-resonant frequencies complement each other, and provide a low impedance to "ground" over a wide frequency range. Bulk capacitance is something of a lesser concern at higher speeds. You might try ceramic caps in the 1uF range, there's a good chance that things will work as well or better, and you could stand to save a buck or more per board. And if you're under an NDA, chances are that you'll be making a few boards

Also, be very wary about "ground," just as an aside. What happens after current magically disappears down the little arrow-esqe symbol in the schematic can make the difference between a functional circuit and a wasted board spin...

If you'd be interested in getting feedback from a more formal venue, PM me--I can probably hook you up.

 

[tex1138]

Xilinx has an excellent appnote about the use of decoupling capacitors. I understand your concern is for an analog circuit, but the theory of decoupling remains the same. A capacitor of a given value in a given package size is going to be most effective over a certain frequency range and a certain distance on the board, so you have to consider the frequency range of interest and lay out your board accordingly.