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greyt_Autumn
Gawd
- Joined
- Oct 2, 2001
- Messages
- 572
About cores and memory access.
We have one core, 2 cores and 4 cores eventually more, currently using the same socket designs.
When these cores access memory, as you scale up the number of cores, are there contention issues (assuming no cache hit)? Is memory (FSB or HT) bandwidth an issue- you now have a dramatically increased need for memory access by the cores and/or their L1 and L2 cache- just by virtue of more work being done.
Do all of the cores access memory on the same channels, or are the designs such that each core has a dedicated access to system ram or at least the memory controller- or is it shared with a 'traffic cop' in between and each core's memory calls get a timeslice?
Are their starvation issues with memory access under 'normal' usage (Assuming that more than one core is doing meaningful work and not laying idle)
Can somebody enlighten me in layman's terms as I'm not an EE let alone very savvy in chip and bus design.
Thanks.
We have one core, 2 cores and 4 cores eventually more, currently using the same socket designs.
When these cores access memory, as you scale up the number of cores, are there contention issues (assuming no cache hit)? Is memory (FSB or HT) bandwidth an issue- you now have a dramatically increased need for memory access by the cores and/or their L1 and L2 cache- just by virtue of more work being done.
Do all of the cores access memory on the same channels, or are the designs such that each core has a dedicated access to system ram or at least the memory controller- or is it shared with a 'traffic cop' in between and each core's memory calls get a timeslice?
Are their starvation issues with memory access under 'normal' usage (Assuming that more than one core is doing meaningful work and not laying idle)
Can somebody enlighten me in layman's terms as I'm not an EE let alone very savvy in chip and bus design.
Thanks.