Haswell and AVX2 extensions

[pxc]

The AVX programming guide has been updated with info about new extensions:
http://software.intel.com/file/36945

1.4 OVERVIEW AVX2
AVX2 extends Intel AVX by promoting most of the 128-bit SIMD integer instructions
with 256-bit numeric processing capabilities. AVX2 instructions follow the same
programming model as AVX instructions.

In addition, AVX2 provide enhanced functionalities for broadcast/permute operations
on data elements, vector shift instructions with variable-shift count per data
element, and instructions to fetch non-contiguous data elements from memory.

That should double integer SIMD throughput on those upgraded instructions.

Haswell is also getting a hardware random number generator.

 

[old skool]

MMX instructions are still retarded even with 256-bit registers.

punpklbw ymm0, ymm0
etc...

 

[pxc]

WOOOOOSH!

Warning: high altitude concept advisory in effect for the preceding post.

 

[darkeen]

And haswell will be after Ivy Bridge?

 

[Rebel44]

And haswell will be after Ivy Bridge?

Correct.

 

[Vexerz]

After Haswell ---> Skynet

 

[pxc]

After Haswell ---> Skynet

LOL, close. Skylake is the next microarchitecture after Haswell.

Haswell ---> Broadwell (14nm shrink) ---> Skylake ---> Skymont (10nm shrink)

Core i14:

Bulldozer 2 is keeping up the good fight in 2025:

[Strike=1]Skylake[/s]Skynet took over GF and forced it to start producing the machines favorite snack: SOI chips. (I'm here all week, folks)

 

[Brahmzy]

Ugh.

LOL

 

[pxc]

More summary info on the Intel blog: http://software.intel.com/en-us/blogs/2011/06/13/haswell-new-instruction-descriptions-now-available/

It also covers new FMA3 instructions in Haswell. AMD added its own FMA4 to Bulldozer CPUs. what a mess.