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Gulftown has 2 x QPI? Source?

R

rflcptr

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Browsing this Wikipedia article and found the part about Gulftown having 2xQPI links. I couldn't find a source for it. Could this allow 2P systems to be built? Or is it only to facilitate communication amongst all the cores?
 
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I assume the 2.4GHz frequency is wrong. I certainly would not pay $1500 US for a 6 core 2.4GHz processor if it was available right now or even last year for that matter. However if that came with a 30% IPC improvement over i7 2.4GHz is fine.
 
Current bloomfields have 2 QPI links (one for chipset one to communicate with the other CPU). Gulftown will be the same one. 1 socket chips have the second QPI disabled.
This shows the die of a bloomfield, in case you wonder how its actually divided.


drescherjm: The frequency is a very early guess. 2.4Ghz has been mentioned before, I doubt Intel even knows what the final retail frequencies will be. edit: and most of the xeon customers will care more about 6/12 cores/threads than the clock speed (and i9 customers will care about it being unlocked multi and 32nm more than default clocks)
 
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Right, but it's specifically stated differently in Gulftown's row than for any of the Bloomfield rows. Why is this?
 
rflcptr said:
Right, but it's specifically stated differently in Gulftown's row than for any of the Bloomfield rows. Why is this?
Click to expand...

Are you serious? You're asking about an unsourced line item in Wikipedia for a future product that no one in the public domain really knows that much about. I could go and change it to 1 x QPI if it give you some peace of mind. :) It would have the exact same amount of credibility.

Both of the sources on that line mention nothing about QPI. Gulftown or whatever code name they use would probably have Xeon version that would be MP capable but the consumer versions tend to have 1 of them disabled, even the 975.
 
Because, as I said, the die will have 2 QPI links. How is this surprising? Ignore the data, draw your own (logical) conclusions. Every die designed for s1366 will have 2 QPI links.

The cores will be slightly modified for AES/32nm enhancements, it'll shrink to 32nm, and it'll be 6 cores wide instead of 4 wide (with 12 instead of 8MB of L3 with the increased width). I don't know how they'll adjust the mem controller circuitry, maybe they'll stick the pieces sideways instead of virtical. extra horizontal space makes that possible. Regardless, they won't waste the die space. But the die shot will be very, VERY similar to the bloomfield above.
 
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