German Researchers Develop Through Silicon Transistors

[AlphaAtlas]

Stacking silicon chips on top of each other and connecting them with micrometer-scale vertical wires was once exotic technology. Nowadays, through silicon vias are found in relatively consumer products, like AMD's Fury and Vega GPUs or in high capacity workstation DDR4. However, researchers in Germany want to take the technology one step farther by building transistors though the vertical layers. The TSVFETS, as Felix Winkler calls them, can be linked up to form larger designs like SRAM memory cells or inverter circuits. However, the researchers also see the new technology being used to protect valuable chip designs.

In addition to adding some control electronics within the interposer, the TSVFET could act as a kind of camouflage to prevent the reverse engineering of a chip or to keep contract manufacturers from producing systems on the sly. Chip designers fear that a foundry contracted to make 1 million chips for a designer might instead make 2 million and secretly sell the other half themselves, explains Winkler. Processors and other complex chips usually have a dozen or more layers of copper interconnects to link the transistors in the silicon together to form circuits. So one solution is to have one foundry build the bottom layers of interconnect and another build the top layers. That way neither manufacturer has the whole design. But a smart interposer, powered by TSVFETs, might be a simpler solution, Winkler argues. One manufacturer could produce all the interconnect layers so long as a different one built the interposer. With its TSVFET-powered logic, the interposer would form a final fail-safe of connections, without which the system wouldn't work.

 

[1_rick]

" Chip designers fear that a foundry contracted to make 1 million chips for a designer might instead make 2 million and secretly sell the other half themselves, explains Winkler."

Gee, I wonder why anyone would think that would happen (SD cards) and who (China) would do it.

 

[dragonstongue]

make complex might keep it "safer" from reverse engineering BUT likely also increase yield issues and per unit cost among other problems that may take place.

Seems like the "next step" to be honest, 3d gates and V-nand or whatever, why not TSV type transistors as well, I wonder if they will make them more of a 3d "style" as well to increase overall transistor density at the same feature size...example 1 billion transistors at 22nm at 45w 2Ghz speed and X latency instead becomes 2 billion at 22nm at 30w 2.8Ghz Y latency (more transistors less per transistor power required and faster operation because they are "closer together)

it might "in theory" also prevent stalls and misses as feature size shrinks and it becomes more and more difficult to keep them coherent without constant stalls and such (I forget what that was called, I read about it a few days ago, this problem is becoming more and more a major issue part of the reason why they are stuffing more and more transistors in chips the further they shrink them to "maintain" expected performance to deal with the much more pronounced "stalls")

Anyways is neat to think about it, to keep one's design "safe" is probably and likely a VERY sticky slope to make it "easy" to do hard for others to replicate but also worth the cost to manage it, am sure it took quite a long time to organize the masks and such for 3d gates, TSV etc, can just imagine how much more per chip cost it would end up being to cram all of those ideas in the same chip while keeping the design on track (look at the massive issues all chip makers had shrinking from 45 to 28 to 16/14nm)

Only going to get harder and harder to do from here on out.