As we've noted in previous articles, manufacturers are quickly hitting the limits of chip shrinking, which means cutting edge processors will increasingly have to turn to advanced packaging solutions (like Intel's "Foveros" and EMIB designs or AMD's chiplet-based products) for performance gains. But in 3D stacked designs, cooling becomes a serious issue, as the top layers of chips effectively insulate the lower layers from heatsinks, and power density increases as more silicon is squeezed into a smaller area. To get around that issue, a group of researchers claim that chip makers could pump distilled water directly through the 3D stacks of future processor designs. The researchers say the approach makes use of gaps that would exist between 3D stacked chips anyway, and that valves could be used to direct more flow to particular chips or zones, while tiny patches of "themoelectric materials" (which typically use electricity to actively pump heat) could thermally link particularly hot areas of the chip to the fluid. The tier-specific cooling approach, compared with conventional microfluidic cooling, can reduce the pumping power by 37.5%, preventing overcooling, when an operating temperature is specified. For anyone who's interested in further reading, the paper also rounds up, and links to, previous microfluidic cooling efforts.