RaphaelVinceti
Gawd
- Joined
- Apr 7, 2005
- Messages
- 600
Are their any Dual Operton motherboards with SLi that dont require Registered ram?
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QFTdefakto said:All opterons require registered ram. It doesn't matter what motherboard you use because the opteron memory controller is on die.
defakto said:If you're going to quote me, seriously, get the entire quote in. I don't mind being proven wrong. No big deal. But no need to be all, "QFT" about it.
Also if you search their forums. Looks like abit pulled the plug on that particular board and alot of their planned server market. That board isn't even mentioned under their 940 boards anymore.
This looks like a promising alternative though
http://www.wideopenwest.com/~AXM77/images/MS-9620.JPG
this link breaks the news about discontinuation of this project
http://techreport.com/onearticle.x/8053
defakto said:Being non-eatx is a good thing though. It will give you a wider ranges of cases that the board will fit in since eatx is typically the largest board you can buy. I agree with you on the ram thing, just depends on the application you want to use the board for really.
defakto said:If you're going to quote me, seriously, get the entire quote in. I don't mind being proven wrong. No big deal. But no need to be all, "QFT" about it.
Also if you search their forums. Looks like abit pulled the plug on that particular board and alot of their planned server market. That board isn't even mentioned under their 940 boards anymore.
This looks like a promising alternative though
http://www.wideopenwest.com/~AXM77/images/MS-9620.JPG
this link breaks the news about discontinuation of this project
http://techreport.com/onearticle.x/8053
defakto said:Not everyone uses 64 bit pci slots....Besides you can put a very nice scsi or sata controller on pci-e
defakto said:Don't get me started on server hardware, I work security in a data center, racks and racks of 15k scsi drives and miles of fiber switches...so neat.
just a few off a quick google search for pci-e drive controllers
pci-e sata raid controller http://www.topmicrousa.com/arc-1220.html
pci-e scsi raid controller http://www.intel.com/design/servers/RAID/srcu42e/
DarkBahamut said:I thought PCI_express connectors were 'closed' at the end, thus an 8x card wouldnt even fit in a lower slots. Could be wrong thought as i dont have a PCI-E mobo, but its what ive seen anyway.
defakto said:Not everyone uses 64 bit pci slots....Besides you can put a very nice scsi or sata controller on pci-e
Sheff said:Getting back to the ram issue, does anyone here run more than 8 Gigs of PC3200 ECC? I'm considering building a rig with K8WE and 16 Gigs and I'm wondering if I'm going to run into any problems. Is it better to get PC2700?
How much memory do you guys have? What brand and what speeds?
in short, its not just how fast you run, but also how long your legs are, a Westy need to run twice as fast as a Wolfhound to cover the same groundGo DeepThe difference in pipeline architectures is what makes a clock-for-clock comparison between the Xeon and Opteron invalid (much like the Pentium 4 to Athlon XP comparison was invalid on a clock-for-clock basis). The Xeon's architecture allows it to reach high clock speeds at the expense of doing less work per clock cycle, the appropriate comparison ends up being one of cost and real-world performance, not one of clock speed.
The more pipeline stages you have, the less work is done per clock and thus the higher you're able to clock your CPU; this is the reason the 20-stage Xeon is currently at speeds of 3GHz, compared to the 12-stage Opteron which is debuting at 1.8GHz.
AMD's 64-bit strategy - x86-64
The benefits of a 64-bit microprocessor architecture are mainly memory related; if you take two identical microprocessors, make one 64-bit and one 32-bit, the advantage of the 64-bit CPU is that it can address much more memory than the 32-bit CPU (2^64 vs. 2^32). For those that were hitting the limits of 32-bit memory addressability (4GB), Intel's only high performance solution was to transition to Itanium, but if all you're looking for is more than 4GB of memory and solid x86 performance, then you're SOL from Intel's perspective.
AMD's 64-bit strategy is significantly different; AMD has always been focused on the current customer needs, not on the vision of the computing future 5 - 10 years from now and this is reflected in their 64-bit strategy. The strategy is simple and has been done before in the past; stick with a high-performing x86 core, and simply extend the ISA to support 64-bit memory addressability - the end result is what AMD likes to call x86-64.
In legacy mode, the K8 will run all native 16 or 32-bit x86 applications, the processor basically acts just as a K7 would.
Things get interesting in "long" mode where a 64-bit x86-64 compliant OS is required; in this mode, the K8 can either operate in full 64-bit mode or in compatibility mode. Full 64-bit mode allows for all of the advantages of a 64-bit architecture to be realized, including 64-bit memory addressability. One of the major features of the K8 architecture is the fact that the number of general purpose registers is doubled when in x86-64 mode, and thus this feature is also taken advantage of in full 64-bit mode.
Compatibility mode gives you none of the advantages of a 64-bit architecture on the application level, as it is designed for running 32-bit apps on a 64-bit OS (hence the name compatibility); The extra registers and 64-bit register extensions are ignored in this mode. Compatibility mode is important because of the 2GB process size limitation under Windows OSes. Although 32-bit Windows offers support for a maximum of 4GB of memory, each process can only use a maximum of 2GB of memory - the remaining 2GB is reserved for the OS. By running a 64-bit version of Windows (when released) and a 32-bit application, compatibility mode allows for each 32-bit process to have up to a full 4GB of memory, with the OS using anything above that marker.
Finally we have 64-bit long mode, where there is more than meets the eye. In addition to > 4GB memory addressability, in 64-bit long mode, applications have access to twice as many named general purpose registers. Remember that registers are basically high speed memory locations on the microprocessor where temporary values are stored. For example, if you were to compute the sum of two numbers, both of those numbers as well as the final result would be stored in these registers.
Look what we found, an on-die memory controller
The benefits of an integrated memory controller are clear - low latency memory accesses and an extremely fast controller design thanks to the fact that it is manufactured using the latest processes using the fastest transistors.
(see chart)
You can see that the integrated memory controller of the Opteron is significantly lower latency than the nForce2's dual-channel DDR memory controller. It is also worth noting that the 875P memory controller is extremely low latency, especially for an external controller - but you have to keep in mind that we're comparing two different clock speed CPUs here when we're comparing to the Intel platform. While the platform may have a latency similar to that of the Opteron, the CPU is running at a much higher frequency meaning that more clock cycles are being wasted in the same amount of time:
(see chart)
The above graph shows the number of clock cycles wasted on waiting for data from main memory, here we see the clear advantage of having an on-die memory controller.
The downside to the on-die memory controller is that in order to get support for new memory technologies, you need to replace your CPU, not just your motherboard. AMD has built functionality into the K8 core that allows an external chipset to disable the on-die memory controller and use an external one. However, remember that a K8 without the integrated memory controller is basically like an optimized K7 with a longer pipeline.
Multiprocessor Mecca
The culmination of all of this is that the K8 core (and thus the Opteron) scales very well with the number of CPUs you have in a system, much better so than any Intel processor.
Whereas the Xeon only sees an 11% increase in performance from going to two CPUs, the Opteron sees an impressive 24% performance boost! These are not numbers to scoff at; AMD has clearly designed the Opteron for serious multiprocessing environments. We hope to be able to bring you 4-way scaling benchmarks very soon.
Another interesting thing about the K8 architecture is that it has already been engineered for use in multicore designs. AMD's Fred Weber mentioned to us that the logic for multicore, single die Opteron processors has already been verified, although nothing has taped out. The process is actually quite simple; AMD produces two Opteron cores, removes the physical layers of the Hyper Transport links and connects the two on a single die.
AMD Opteron vs. Intel Xeon: Database Performance Shootout
Future Xeon and Pentium 4 processors will ship with the x86-64 extensions enabled but architecturally they will be identical to the currently available Prescott based Pentium 4. The architectural similarity between Intel's IA-32e ad IA-32 processors (IA-32e is Intel's marketing equivalent to AMD64) is an important point to note as it means that if Opteron is able to outperform Xeon in 32-bit mode, it will maintain a performance advantage in 64-bit mode as well.
FSB Impact on Performance: Intel's Achilles' Heel
We've alluded to FSB bandwidth being a fundamental limitation in Intel's multiprocessor architecture, and now we're here to address the issue a bit further.
A major downside to Intel's reliance on an external North Bridge is that it becomes very expensive to implement multiple high speed FSB interfaces as well as a difficult engineering problem to solve once you grow beyond 2-way configurations. Unfortunately Intel's solution isn't a very elegant one; regardless of whether you're running 1, 2 or 4 Xeon processors they all share the same 64-bit FSB connection to the North Bridge.
The following diagram should help illustrate the bottleneck
(see chart)
In the case of a 4-way Xeon MP system with a 400MHz FSB, each processor can be offered a maximum of 800MB/s of bandwidth to the North Bridge. If you try running a single processor Pentium 4 3.0GHz with a 400MHz FSB you'll note a significant performance decrease and that's while still giving the processor a full 3.2GB/s of FSB bandwidth; now if you cut that down to 800MB/s the performance of the processor would suffer tremendously.
It is because of this limitation that Intel must rely on larger on-die L3 caches to hide the FSB bottleneck; the more information that can be stored locally in the Xeon's on-die cache, the less frequently the Xeon must request for data to be sent over the heavily trafficked FSB.
What's even worse about this shared FSB is that the problem grows larger as you increase the number of CPUs and their clock speed. A 2-way Xeon system won't experience the negative effects of this FSB bottleneck as much as a 4-way Xeon MP; and a 4-way Xeon MP running at 3GHz will be hurting even more than a 4-way 2.0GHz Xeon MP. It's not a nice situation to be in, but there's nothing you can do to skirt the issue, which is where AMD's solution begins to appear to be much more appealing:
(see chart)
First remember that each Opteron has its own on-die North Bridge and memory controller, so there are no external chipsets to deal with. Each Opteron CPU features three point-to-point Hyper Transport links, delivering 3.2GB/s of bandwidth in each direction (6.4GB/s full duplex). The advantage is clear: as you scale the number of CPUs in an Opteron server there are no FSB bottlenecks to worry about. Scalability on the Opteron is king, which is the result of designing the platform first and foremost for enterprise level server applications.
Intel may be able to add 64-bit extensions to their Xeon MPs, but the performance bottlenecks that exist today will continue to plague the Xeon line until there's a fundamental architecture change.
This is what was attached to Tyan's latest BIOS update for the k8w:defakto said:Depends on the board I believe. I think the thunder k8w, once you pass the 4 gig barrier, will default down to pc2700 speeds from higher clocked ram.
So you really only need to worry if you have a CG or older core.[font=Verdana,Tahoma,Arial,Helvetica][size=-2]# [/size][/font][font=Verdana,Tahoma,Arial,Helvetica]Note: This BIOS follows AMD recommendations for DDR bus speed as a function of loading. As a result if you are running CG or older stepping CPU AND more than 6 loads DDR 400 memory the BIOS will automatically set the bus speed to DDR 333 speeds. For more information see the AMD BIOS and Kernel Developer's Guide (PID# 26094)[/font]
Hi, Sorry, we don't currently support XP64 in any of our products. -Support