CPU multipliers, Technical Understanding

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YARDofSTUF

[H]ard|Gawd
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Jun 19, 2001
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I'm in school for my A+, Security +, and MCP 270-90(or whatever the XP one is) and the A+ book is horrible at explaining the multiplier's relationship in the cpu,

The book says a P4C at 3.2ghz has a multi of 4, because the bus speed is 800mhz.

The book draws a CPU's components(Registers, ALUs, Internal Cache, Control Unit, I/O Unit) and I was wondering how to factor the multiplier correctly into this, or at least explain it correctly.
 
the book is wrong.
It's a 200mhz bus, with 4 data packets per clock cycle (quad-pumped). Meaning you need a 16x multipler to get 3.2ghz from that.
DDR / Quadpumped whatever do not effect the frequency that's being multiplied. The actual clock speed * CPU multiplier is the resulting CPU clock speed.

The book draws a CPU's components(Registers, ALUs, Internal Cache, Control Unit, I/O Unit) and I was wondering how to factor the multiplier correctly into this, or at least explain it correctly.
Click to expand...


I'm not sure I understand, in all but a few cases those parts are all running at the CPU speed.
 
FreiDOg said:
I'm not sure I understand, in all but a few cases those parts are all running at the CPU speed.
Click to expand...


In a drawing where whould the multiplier chip be, what would it be called? is it not inside the cpu?
 
The multiplier is not a physical part of the chip...it is just an arbitrary number that the host clock is multiplied by to get the internal cpu clock. They're typically set by a series of bridges on the surface of the cpu that are either connected or cut to make a particular sequence. The mobo then reads that sequence off the cpu and sets the cpu clock speed accordingly.

Also as Freidog mentioned almost every part of the cpu will be running at cpu clock speed. The only exceptions I can think of are the ALU's in netburst chips (like your example P4) which run at twice the cpu clock, and the FPU's in older via C3's which ran at half cpu clock speed.
 
Eva_Unit_0 said:
The multiplier is not a physical part of the chip...it is just an arbitrary number that the host clock is multiplied by to get the internal cpu clock. They're typically set by a series of bridges on the surface of the cpu that are either connected or cut to make a particular sequence. The mobo then reads that sequence off the cpu and sets the cpu clock speed accordingly.
Click to expand...

Actually it kind of is.
The multiplier itself is rather trivial, but it's a vital part of a chip's clock generator.

Chips use a phase locked loop (PLL) to drive the rather large capacitance of a global clock signal and still keep it 'in phase' with the FSB. The multiplier is part of that circuitry. A PLL with a divide by N counter on the feedback line outputs N clock cycles for every clock cycle on the input. Or, it's running with a multiplier of N.
To use the example of the 3.2ghz P4, the input would be 200mhz and the PLL would be using a divide by 16 counter. So 16 CPU cycles would correspond to 1 cycle on the feedback line, and the PLL would sync the feedback to the input.

This is actualy the reason you can't have a CPU multiplier like 10.25 or 7.33. The divide by N counter can only count state changes, of which there are just two per clock cycle (0 to 1 and 1 to 0). You can't get any finer adjustments than half a clock cycle.
 
FreiDOg said:
Actually it kind of is.
The multiplier itself is rather trivial, but it's a vital part of a chip's clock generator.

Chips use a phase locked loop (PLL) to drive the rather large capacitance of a global clock signal and still keep it 'in phase' with the FSB. The multiplier is part of that circuitry. A PLL with a divide by N counter on the feedback line outputs N clock cycles for every clock cycle on the input. Or, it's running with a multiplier of N.
To use the example of the 3.2ghz P4, the input would be 200mhz and the PLL would be using a divide by 16 counter. So 16 CPU cycles would correspond to 1 cycle on the feedback line, and the PLL would sync the feedback to the input.

This is actualy the reason you can't have a CPU multiplier like 10.25 or 7.33. The divide by N counter can only count state changes, of which there are just two per clock cycle (0 to 1 and 1 to 0). You can't get any finer adjustments than half a clock cycle.
Click to expand...

hmmm well fancy that. I guess maybe next quarter when I take IC Tech and Circuits 1 I'll see that in action...or maybe the next one when I take Semiconductor Devices 1.
 
FreiDOg said:
Actually it kind of is.
The multiplier itself is rather trivial, but it's a vital part of a chip's clock generator.

Chips use a phase locked loop (PLL) to drive the rather large capacitance of a global clock signal and still keep it 'in phase' with the FSB. The multiplier is part of that circuitry. A PLL with a divide by N counter on the feedback line outputs N clock cycles for every clock cycle on the input. Or, it's running with a multiplier of N.
To use the example of the 3.2ghz P4, the input would be 200mhz and the PLL would be using a divide by 16 counter. So 16 CPU cycles would correspond to 1 cycle on the feedback line, and the PLL would sync the feedback to the input.

This is actualy the reason you can't have a CPU multiplier like 10.25 or 7.33. The divide by N counter can only count state changes, of which there are just two per clock cycle (0 to 1 and 1 to 0). You can't get any finer adjustments than half a clock cycle.
Click to expand...

Now is this set on a chip in the cpu or on the motherboard?
 
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