Conroe debunked

[Donnie27]

well.. the "way" a cache is implemented does matter.. but the determining factor of whether you perform better or not is in the actual code being runned..

But, i'm sure intel does massive amounts of cache simulations running different type of benchmarks and such to determine like an optimal cache configuration for across the board gain.. as opposed to gains in some types of a programs, and loses in others.. so in the end to the average user.. there will be a performancing gain...

but i guess this is just getting into garbage that isn't really important..

Sorry, I disagree. Yes the app's code is important but that's not what I meant. Intel's Conroe is Smarter, here read this.

http://www.pcper.com/article.php?aid=217&type=expert&pid=4

It can help when bad code is used, it can mask letency of the on chip mem controller and
etc.......

Advanced Smart Cache

First, the cache is shared between the cores but it is not statically allocated to either core in any fashion. The amount of L2 cache that is being controlled by either core can be adjusted dynamically when one core is in need of more of it than the other. If only a single thread is being executed in the operating system, the primary core can take more of the L2 cache and use it to lower the memory latency hit, thus preventing the “cache thrashing” when cache is full and the CPU has to go to main system memory.

So depending on usage, one core could use all 4MB of cache or divy up cache as needed between the two cores. Yes, it can increase performance in both instances. Example, Q3 Time Demo can be ran completely from L2 and almost never touching main memory.

 

[GilmourD]

It can help when bad code is used, it can mask letency of the on chip mem controller and
etc.......

LOL Oh, now Conroe suddenly has a memory controller? LOL

 

[Donnie27]

LOL Oh, now Conroe suddenly has a memory controller? LOL

Nothbridge = Chip, not on die LOL! Please at least take the time to read the link before you blink? You'd see that the cache has a way of hiding latency, L2 to System Memory via the Mem controller built into the Northbridge.

Smart Memory Access and Smart Cache

Smart Memory Access

Now, before you start to ask, Intel did not include an integrated memory controller on the Core Architecture for many reasons (they discussed those reasons with me but I was asked to keep this information confidential). But the new memory access specifications on this design do a good job of hiding the latency that an external memory controller introduces versus an integrated one.

 

[Mav451]

Sorry, I disagree. Yes the app's code is important but that's not what I meant. Intel's Conroe is Smarter, here read this.

http://www.pcper.com/article.php?aid=217&type=expert&pid=4

It can help when bad code is used, it can mask letency of the on chip mem controller and
etc.......

Advanced Smart Cache

First, the cache is shared between the cores but it is not statically allocated to either core in any fashion. The amount of L2 cache that is being controlled by either core can be adjusted dynamically when one core is in need of more of it than the other. If only a single thread is being executed in the operating system, the primary core can take more of the L2 cache and use it to lower the memory latency hit, thus preventing the “cache thrashing” when cache is full and the CPU has to go to main system memory.

So depending on usage, one core could use all 4MB of cache or divy up cache as needed between the two cores. Yes, it can increase performance in both instances. Example, Q3 Time Demo can be ran completely from L2 and almost never touching main memory.

Sounds pretty nice. I wonder how much this is responsible for performance gains in gaming =D.

 

[GilmourD]

Nothbridge = Chip, not on die LOL! Please at least take the time to read the link before you blink? You'd see that the cache has a way of hiding L2 to System Memory via the Mem controller built into the Northbridge.

Smart Memory Access and Smart Cache

Smart Memory Access

Now, before you start to ask, Intel did not include an integrated memory controller on the Core Architecture for many reasons (they discussed those reasons with me but I was asked to keep this information confidential). But the new memory access specifications on this design do a good job of hiding the latency that an external memory controller introduces versus an integrated one.

I did. You said

Originally Posted by Donnie27
It can help when bad code is used, it can mask letency of the on chip mem controller and
etc.......

Write what you mean and mean what you write. And now Intel is discussing things directly with you? Did I miss the part where you became important enough to get confidential information? I dunno... My bullshit detector's starting to ping.

 

[Donnie27]

Sounds pretty nice. I wonder how much this is responsible for performance gains in gaming =D.

I'm no expert but it sounds like it has a lot to do with gains made during those gaming benchmarks. IMHO, what Intel is saying or seems to be saying, is that this is a work around to hide latency caused by NOT having an Intragrated memory controller. Or a better way to do it without the costs and etc. of having an integrated memory controller. Take your pick?

 

[Donnie27]

I did. You said
Write what you mean and mean what you write. And now Intel is discussing things directly with you? Did I miss the part where you became important enough to get confidential information? I dunno... My bullshit detector's starting to ping.

I said CHIP not DIE!

 

[(cf)Eclipse]

Now, before you start to ask, Intel did not include an integrated memory controller on the Core Architecture for many reasons (they discussed those reasons with me but I was asked to keep this information confidential). But the new memory access specifications on this design do a good job of hiding the latency that an external memory controller introduces versus an integrated one.[/I]

no matter what you do to the cpu, memory latency is memory latency.

 

[GilmourD]

I said CHIP not DIE!

Common vernacular for "die" is "chip". And is the memory controller anywhere in the Conroe package? If not, then it's still the standard CPU/chipset relationship that everything (besides the Athlon64 and Cyrix MediaGX) uses, and the Conroe is blind to memory performance.

 

[(cf)Eclipse]

and the Conroe is blind to memory performance.

i think you should be a bit more explicit here, it's blind to the ram, as long as it gets what it wants quickly.

 

[Donnie27]

no matter what you do to the cpu, memory latency is memory latency.

They're not talking about memory latency. They're talking about the latency between L2/Core and the Memory Controller, not what happens after the memory controller, be it CHIPset or On Die based. AMD went to an On-Die memory controller like Alpha used. Intel having Fabbed some of those chips didn't want to go that route. Now they seemed to have found a work around.

Again, if the other guy had read the link, he'd have seen this;

"Now, before you start to ask, Intel did not include an integrated memory controller on the Core Architecture for many reasons (they discussed those reasons with me but I was asked to keep this information confidential). But the new memory access specifications on this design do a good job of hiding the latency that an external memory controller introduces versus an integrated

Then I wouldn't get asked stupid questions like, "Did I miss the part where you became important enough to get confidential information?" This is the same Ryan Shrout. that Tom's hardware called an AMD worshipper while their site was AMDmb.com. Hardly and Intel Fan.

http://www.pcper.com/article.php?aid=25

 

[GilmourD]

i think you should be a bit more explicit here, it's blind to the ram, as long as it gets what it wants quickly.

Which it is getting from the chipset. As long as the chipset is pumping out enough data for the CPU, then what does the CPU care about bandwidth between the chipset and memory?

 

[Donnie27]

Common vernacular for "die" is "chip". And is the memory controller anywhere in the Conroe package? If not, then it's still the standard CPU/chipset relationship that everything (besides the Athlon64 and Cyrix MediaGX) uses, and the Conroe is blind to memory performance.

Not in this context if you read the link. Then you'd know that Chip in that case meant Chipset and not Die-Set, sheesh! Then you know why Conroe is mostly blind to Memory performance because the improvements are made prior to cache trashing and the system going to memory

 

[GilmourD]

Then I wouldn't get asked stupid questions like, "Did I miss the part where you became important enough to get confidential information?" This is the same Ryan Shrout. that Tom's hardware called an AMD worshipper while their site was AMDmb.com. Hardly and Intel Fan.

http://www.pcper.com/article.php?aid=25

Well, somebody needs to learn how to quote and notate sources. If you read what you said above, there were no quotation marks or sufficient indication that you were using somebody else's words, therefore, one would think that they were your words. Sorry I didn't memorize the article you referred to in another post previous to that post to realize.

 

[Donnie27]

Which it is getting from the chipset. As long as the chipset is pumping out enough data for the CPU, then what does the CPU care about bandwidth between the chipset and memory?

Shakes head and gives up.

 

[GilmourD]

Shakes head and gives up.

You didn't answer my question.

 

[(cf)Eclipse]

Shakes head and gives up.

no seriously, try your best to explain it.. to me even, because what i think you're trying to say is just wrong. it was similar to terra's argument about RDRAM and how the P4 was designed for it. i said that with any given workload, a certain set of data must have work done on it. no matter how the cpu is set up, that workload and data set will always be the same. only way more bandwidth or lower latency is needed is if the cpu goes through the workload faster.

 

[ToastMaster]

They're not talking about memory latency. They're talking about the latency between L2/Core and the Memory Controller, not what happens after the memory controller, be it CHIPset or On Die based. AMD went to an On-Die memory controller like Alpha used. Intel having Fabbed some of those chips didn't want to go that route. Now they seemed to have found a work around.

Again, if the other guy had read the link, he'd have seen this;



Then I wouldn't get asked stupid questions like, "Did I miss the part where you became important enough to get confidential information?" This is the same Ryan Shrout. that Tom's hardware called an AMD worshipper while their site was AMDmb.com. Hardly and Intel Fan.

http://www.pcper.com/article.php?aid=25

No, they're not talking about the latency of the L2 cache to the Core, and then to the memory controller. Conroe doesn't have a true "memory controller" in the sense that the A64 series does. The latency is between the core itself, and the speed at which the FSB can access the DDRII. There is also then a latency betwen the core and the L2 cache, and it's this latency of the cache between dual cores, that Conroe is good at hiding.

And I have never heard of Intel having done any type of ES-work on chips with integrated memory controllers. I have heard where they conceptually studied it, but in the end decided to stick with the FSB. A fab out of IMC-based chips? Never happened.

 

[ToastMaster]

Not in this context if you read the link. Then you'd know that Chip in that case meant Chipset and not Die-Set, sheesh! Then you know why Conroe is mostly blind to Memory performance because the improvements are made prior to cache trashing and the system going to memory

For all a Conroe chip cares, it could be using a high-speed form of RD-RAM ,as l;ong as the memory is able to deliver enough bandwidth to the processor.

Conroe's L2 cache has nothing to do with what memory type is used. These are two completely different branches of the same tree.

 

[Donnie27]

No, they're not talking about the latency of the L2 cache to the Core, and then to the memory controller. Conroe doesn't have a true "memory controller" in the sense that the A64 series does. The latency is between the core itself, and the speed at which the FSB can access the DDRII. There is also then a latency betwen the core and the L2 cache, and it's this latency of the cache between dual cores, that Conroe is good at hiding.

And I have never heard of Intel having done any type of ES-work on chips with integrated memory controllers. I have heard where they conceptually studied it, but in the end decided to stick with the FSB. A fab out of IMC-based chips? Never happened.

Intel's Memory Controller is Integrated into the Northbridge as part of the Chipset=P This has higher latency than Alpha's and or AMD's integrated memory conrtollers. To mask the Higher latency of this Northbridge based Memory Controller, Intel came up with Smart Cache and Smart Memory Access. OK?

Now I absolutely know Conroe doesn't have an On-Die memory conroller and the Memory Controller is built into the Northbridge. Conroe Doesn't contain Cross bar or Hypertransport while I'm at it.

Here's what I quoted.

Now, before you start to ask, Intel did not include an integrated memory controller on the Core Architecture for many reasons (they discussed those reasons with me but I was asked to keep this information confidential). But the new memory access specifications on this design do a good job of hiding the latency that an external memory controller introduces versus an integrated one.

Bold and underlined to make a point.

And

Also with this integration of a shared cache, the two cores can very easily share data in multi-threaded applications. They no longer have to go out onto the front-side bus like on older Intel architectures or over a data crossbar like we see on the AMD Athlon architecture.

Might also need to click on "Detailed Preview".

Intel demoed a Processor (system on a Chip) with not only a Memory controller, but Audio, Video, NIC and Voltage regualation controllers as well LOL! I'm not talking about Timna either. I linked folks to a smaller version last week.

 

[Poncho]

Intel demoed a Processor (system on a Chip) with not only a Memory controller, but Audio, Video, NIC and Voltage regualation controllers as well LOL! I'm not talking about Timna either. I linked folks to a smaller version last week.

I've talked with some of the people are are working on this... they are doing some wicked cool shit. Really bleeding edge stuff. Very cool.

 

[ToastMaster]

Intel's Memory Controller is Integrated into the Northbridge as part of the Chipset=P This has higher latency than Alpha's and or AMD's integrated memory conrtollers. To mask the Higher latency of this Northbridge based Memory Controller, Intel came up with Smart Cache and Smart Memory Access. OK?

Now I absolutely know Conroe doesn't have an On-Die memory conroller and the Memory Controller is built into the Northbridge. Conroe Doesn't contain Cross bar or Hypertransport while I'm at it.

But see, that's just it. Cache can do very little to actually "hide" the latency of a external memory controller. What that guy is stating, is that they changed the way that the core of Conroe itself accesses the DDRII, so that it attempts to hide this latency. That is what Smart Memory Access is. Smart Cache is hardly related to this, but is, as Intel's own website states: "Intel® Advanced Smart Cache
The Intel® Advanced Smart Cache is a multi-core optimized cache that significantly reduces latency to frequently used data, thus improving performance and efficiency by increasing the probability that each execution core of a dual-core processor can access data from a higher-performance, more efficient cache subsystem.".

Smart Cache hides latencies of the cache itself, between the cores. It does nothing concerning access of external DDRII ram. That is party what Smart Memory Access is for.

Intel demoed a Processor (system on a Chip) with not only a Memory controller, but Audio, Video, NIC and Voltage regualation controllers as well LOL! I'm not talking about Timna either. I linked folks to a smaller version last week.

Have a link? Even if they did do that (and it wouldn't be anything new, Cyrix did it several years ago ultimately), it doen't mean it "fabbed out", so to speak.

 

[Donnie27]

I've talked with some of the people are are working on this... they are doing some wicked cool shit. Really bleeding edge stuff. Very cool.

Yes, now if I could remember that Link, hehehehe!

 

[ToastMaster]

What I find really interesting, from Intel's website, is this:

"Intel Smart Memory Access includes an important new capability called "memory disambiguation," which increases the efficiency of out-of-order processing by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute before all previous store instructions are executed."

They're already looking to what is possibly going to be their greatest performance threat - Cell. With Sony using it in the PS3 (having worked with IBM and others on it), and I've heard AMD is looking into it with IBM (as the two are close partners), it could very well be that Intel is positioning Conroe to attempt to fight Cell, as Cell is known to be very efficient, as long as it's programmed for in-order processing (far more effficient than x86-based systems, if I recall correctly).

 

[GilmourD]

Have a link? Even if they did do that (and it wouldn't be anything new, Cyrix did it several years ago ultimately), it doen't mean it "fabbed out", so to speak.

Yep, as I mentioned before, it's called the Cyrix MediaGX.

 

[Donnie27]

But see, that's just it. Cache can do very little to actually "hide" the latency of a external memory controller. What that guy is stating, is that they changed the way that the core of Conroe itself accesses the DDRII, so that it attempts to hide this latency. That is what Smart Memory Access is. Smart Cache is hardly related to this, but is, as Intel's own website states: "Intel® Advanced Smart Cache
The Intel® Advanced Smart Cache is a multi-core optimized cache that significantly reduces latency to frequently used data, thus improving performance and efficiency by increasing the probability that each execution core of a dual-core processor can access data from a higher-performance, more efficient cache subsystem.".

Smart Cache hides latencies of the cache itself, between the cores. It does nothing concerning access of external DDRII ram. That is party what Smart Memory Access is for.

Have a link? Even if they did do that (and it wouldn't be anything new, Cyrix did it several years ago ultimately), it doen't mean it "fabbed out", so to speak.

First of all, I'm thinking both has something do with it, not just one thing, or else I agree. It akes both of these improvements as a work around to make up for not havingan Integrated Memory Controller.

Nope I don't have the link. Poncho is an Intel employee and knows what I'm talking about. I will look for the link this time instead of brushing anyone off.

 

[Donnie27]

Yep, as I mentioned before, it's called the Cyrix MediaGX.

Not what I'm talking about, hell I could have said Timna but didn't.

 

[Donnie27]

What I find really interesting, from Intel's website, is this:

"Intel Smart Memory Access includes an important new capability called "memory disambiguation," which increases the efficiency of out-of-order processing by providing the execution cores with the built-in intelligence to speculatively load data for instructions that are about to execute before all previous store instructions are executed."

They're already looking to what is possibly going to be their greatest performance threat - Cell. With Sony using it in the PS3 (having worked with IBM and others on it), and I've heard AMD is looking into it with IBM (as the two are close partners), it could very well be that Intel is positioning Conroe to attempt to fight Cell, as Cell is known to be very efficient, as long as it's programmed for in-order processing (far more effficient than x86-based systems, if I recall correctly).

Good points, off to search!

 

[ToastMaster]

Yep, as I mentioned before, it's called the Cyrix MediaGX.

yeah, I know. I still have a Cyrix MediaGX-based desktop at home, 233Mhz. Granted, it hasn't been used in several years, but I should fire it up sometime.

 

[ToastMaster]

First of all, I'm thinking both has something do with it, not just one thing, or else I agree. It akes both of these improvements as a work around to make up for not havingan Integrated Memory Controller.

Nope I don't have the link. Poncho is an Intel employee and knows what I'm talking about. I will look for the link this time instead of brushing anyone off.

I don't think it's so much of a workaround, as it is simply a very technical "trick" (and I hate using that word for this, but it's the best I can think of at the moment to apply) to extend the life of the FSB (where Smart Memory Access is concerned). The Smart Cache is simply because it's cheaper to implement a shared cache, and then design it to very efficiently be shared between two cores, than to give each core it's own cache (such as like what AMD and the Netburst-based dual cores use). That having been said, it'll be interesting to see how this holds up for the small-cached Conroes in multitasking-heavy environments. I don't think we've truly seen any benchmarks yet run by anyone that truly stresses Conroe in multitasking environments. Would be a good reequest for the XS members who have ES Conroes.

 

[GilmourD]

yeah, I know. I still have a Cyrix MediaGX-based desktop at home, 233Mhz. Granted, it hasn't been used in several years, but I should fire it up sometime.

Considering it is a Cyrix, just hope that the fire part isn't literal. LOL

 

[ToastMaster]

Considering it is a Cyrix, just hope that the fire part isn't literal. LOL

Honestly, it was a halfway-decent chip. I mean, it obviously wasn't as fast as the Pentium IIs or the Pentium Pros, but it served me well (I recieved it as my graduation gift from gradeschool, going into high school) for a couple of years, until I got a P3-based system.

 

[duby229]

I don't think it's so much of a workaround, as it is simply a very technical "trick" (and I hate using that word for this, but it's the best I can think of at the moment to apply) to extend the life of the FSB (where Smart Memory Access is concerned). The Smart Cache is simply because it's cheaper to implement a shared cache, and then design it to very efficiently be shared between two cores, than to give each core it's own cache (such as like what AMD and the Netburst-based dual cores use). That having been said, it'll be interesting to see how this holds up for the small-cached Conroes in multitasking-heavy environments. I don't think we've truly seen any benchmarks yet run by anyone that truly stresses Conroe in multitasking environments. Would be a good reequest for the XS members who have ES Conroes.

I'm pretty sure Netburst used a shared cache as well.

This new thing is simply a marketing gimmick. It is just a name for an old hack. Yes that is right hack....

Trust me "hack" is a better word....

 

[ToastMaster]

I'm pretty sure Netburst used a shared cache as well.

This new thing is simply a marketing gimmick. It is just a name for an old hack. Yes that is right hack....

Trust me "hack" is a better word....

Netburst didn't use shared cache. The only thing Netburst is guilty of, is that Intel went the quick and dirty way of dual-core implementation, and simply slapped two separate cores onto a single chip. The result was two separate cores, each with their own cache, that had to use the FSB to communicate. It wasn't the most efficient of designs, obviously, but it works decently.

 

[ToastMaster]

I'm pretty sure Netburst used a shared cache as well.

This new thing is simply a marketing gimmick. It is just a name for an old hack. Yes that is right hack....

Trust me "hack" is a better word....

oh, and I don't honestly think that it's actually a "hack", or a marketing gimmick. I think Intel did a good job in how they implemented the new memory access technology. Granted, I'm not a big fan of the FSB (I think it's time should have been over by now), but looking at the performance that Conroe has so far previewed, they're sucking the FSB for all it's worth.

the only thing that does somewhat annoy me, is their cache plan. I wish they would have simply have had each core had its own cache, and then implemented some form of smart cache access for each core, as well as allowing the cache's to link, as they have it now, when required. But, what can you do. :/

 

[Donnie27]

I don't think it's so much of a workaround, as it is simply a very technical "trick" (and I hate using that word for this, but it's the best I can think of at the moment to apply) to extend the life of the FSB (where Smart Memory Access is concerned).

It's almost what Intel said themselves though. If they truely felt they needed it for the desktop, they'd have used it by now. I'd believe you more if you called it that other bad word, FIX than a trick. A trick denotes something is not real and a Gimmick just means PR. This is real and it works, so it neither of those.

The Smart Cache is simply because it's cheaper to implement a shared cache, and then design it to very efficiently be shared between two cores, than to give each core it's own cache (such as like what AMD and the Netburst-based dual cores use).

That sounds backwards. Using a crossbar would be the easiest, since the two cores connect to it and it does the rest. Video cards already had that down pat. One of the good things about a FSB (I agree, I'm tired of it as well) is that it is flexible enough to do more with it. Conroe's was the hardest and the way it is used couldn't been that easy or IBM and AMD would have done it already.

That having been said, it'll be interesting to see how this holds up for the small-cached Conroes in multitasking-heavy environments. I don't think we've truly seen any benchmarks yet run by anyone that truly stresses Conroe in multitasking environments. Would be a good reequest for the XS members who have ES Conroes.

Keep in mind that small cache Conroe still has the same 2MB L2 as AM2/A64 and Opterons with 2MB and more than the other Athlon X2s that ships with 2 X 512K. Back to what started all of this. It isn't the L2's size but how it's used.

 

[Donnie27]

I'm pretty sure Netburst used a shared cache as well.

This new thing is simply a marketing gimmick. It is just a name for an old hack. Yes that is right hack....

Trust me "hack" is a better word....

Netburst never used a Shared L2=P

 

[ToastMaster]

Keep in mind that small cache Conroe still has the same 2MB L2 as AM2/A64 and Opterons with 2MB and more than the other Athlon X2s that ships with 2 X 512K. Back to what started all of this. It isn't the L2's size but how it's used.

Keep in mind also that Conroe has the Smart Cache ability, and we've yet to really see benchmarks that truly press cache to the extreme.

And you're right, it is how it's used. So far, we've mostly seen benchmarks that primarily make use of a single core, and thus that cache is largely available to the core that is doing the work.

I honestly want to see some benchmarks that make use of multitasking extensively, so we can see how Conroe's Smart Cache can hold up to dual-core, cache-demanding operations.

 

[Donnie27]

Keep in mind also that Conroe has the Smart Cache ability, and we've yet to really see benchmarks that truly press cache to the extreme.

And you're right, it is how it's used. So far, we've mostly seen benchmarks that primarily make use of a single core, and thus that cache is largely available to the core that is doing the work.

I honestly want to see some benchmarks that make use of multitasking extensively, so we can see how Conroe's Smart Cache can hold up to dual-core, cache-demanding operations.

I agree!

 

[RancidWAnnaRIot]

Sorry, I disagree. Yes the app's code is important but that's not what I meant. Intel's Conroe is Smarter, here read this.

http://www.pcper.com/article.php?aid=217&type=expert&pid=4

It can help when bad code is used, it can mask letency of the on chip mem controller and
etc.......

Advanced Smart Cache

First, the cache is shared between the cores but it is not statically allocated to either core in any fashion. The amount of L2 cache that is being controlled by either core can be adjusted dynamically when one core is in need of more of it than the other. If only a single thread is being executed in the operating system, the primary core can take more of the L2 cache and use it to lower the memory latency hit, thus preventing the “cache thrashing” when cache is full and the CPU has to go to main system memory.

So depending on usage, one core could use all 4MB of cache or divy up cache as needed between the two cores. Yes, it can increase performance in both instances. Example, Q3 Time Demo can be ran completely from L2 and almost never touching main memory.

well yeah.. lol... you're right.. hehe there are always tricks that can be implemented... i'm not expert on intel CPUs.. i was just talking from general knowledge about cache.. general knowledge on cache basics anyway..