Big Navi

erek

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It's coming! 2020!

"Lisa Su in August 2019 during the second-quarter earnings call (story):

Q: Can you give us a sense on 7nm high-end NAVI and mobile 7nm CPUs

A: You asked a good product question. I would say they are coming. You should expect that our execution on those are on track and we have a rich 7nm portfolio beyond the products that we have already announced in the upcoming quarters."


 
HBM for consumer GPUs is not happening

As long as Nvidia use GDDR6 they will have AMD for lunch in terms of cost, if AMD go alone on the HBM path for consumer GPUs

They've already had 2 (RX Fury and RX Vega 56/64) -- why not another?
ETA: Actually 3 (Radeon VII)
 
They've already had 2 (RX Fury and RX Vega 56/64) -- why not another?
ETA: Actually 3 (Radeon VII)

The price of the Radeon VII !!!

Strictly for those who needed that large memory (not needed/beneficial for gaming)
 
Big Navi will have HBM2E. AMD codeveloped it to use it on their high end parts. Its not as expensive as it was. The tech has matured and it is a better solution vs 4 - 8 GDDR6 chips throwing heat all over the place.
 
Big Navi will have HBM2E. AMD codeveloped it to use it on their high end parts. Its not as expensive as it was. The tech has matured and it is a better solution vs 4 - 8 GDDR6 chips throwing heat all over the place.

So they're going to spend shit loads of money reworking Navi's memory controller to support HBM for....Reasons?
 
So they're going to spend shit loads of money reworking Navi's memory controller to support HBM for....Reasons?

If the commerial parts use HBM for big Navi it wouldn’t require rework.
 
So they're going to spend shit loads of money reworking Navi's memory controller to support HBM for....Reasons?


Exactly. After spending all this time working with Big Navi on GDDR6 consoles, do you really think they're going to have the time to switch to HBM2E?

You can run the 5700-equivelent performance (5600 XT overclock) on 192-bit 14 Gbps ram, so doubling core count and bus width should scale just fine.
 
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Big Navi is RDNA2 , so I guess we can call it a refresh or simply a step towards the higher end parts ;)
 
People need to get over there hard on for HBM, just because it may be technically superior on paper, doesn’t mean it unlocks hidden performance compared to GDDR. Current gen GPUs simply aren’t saturating the bandwidth which is why overclocking memory nets almost no benefit because guess what, overclocking memory, increases bandwidth.
 
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Right, had nvidia used it on their mainstream cards it would be ok. Superior on paper. Typical...!
 
Good. Glad that died quickly. HBM2e would drive price even higher than I fear it would be.

I'm hoping for some specs to be released on March 5th. I am resigned to just seeing a graphic with an "RDNA2" logo on an upswinging graph with some buzzwords pasted around it.
 
Wont matter too much if they dont get their drivers working properly first.

Even Nvidia has problems with that they do a good job but if you read the Nvidia forums it's laughable like Chief Blur Buster mentioned.
At least Sora is buried in the mess.
 
Wont matter too much if they dont get their drivers working properly first.


What you mean "get drivers working first?"

Remember when Vega was just a Fury X die shrink/addition of Polaris enhancements + 16-bit FP + HBM2?

Those changes were enough to crater the Vega driver program at Unstable for a full twelve months! And this was separate issues from Polaris (was stable after 6 months).

If you're completely revamping the architecture, expect at least 6-12 months of driver pains for Big Navi.
 
What you mean "get drivers working first?"

Remember when Vega was just a Fury X die shrink/addition of Polaris enhancements + 16-bit FP + HBM2?

Those changes were enough to crater the Vega driver program at Unstable for a full twelve months! And this was separate issues from Polaris (was stable after 6 months).

If you're completely revamping the architecture, expect at least 6-12 months of driver pains for Big Navi.

I seriously hope not, because that would just be fucking depressing.
 
The HBM question is simple. When they design a GPU they design it for a specific amount of memory bandwidth. If that number is not achievable on GDDR6 they will do HBM. It's that simple.

Now, where is that cutoff? Well, it depends on if you think a 512-bit GDDR6 bus is realistic or not. Given 16Gbit GDDR6 is the fastest available that gives you 768GB/sec for 384bit, and 1024GB/sec for 512bit (if 512bit is possible -- which it probably isn't).


EDIT: I suppose 18Gbit GDDR6 is available now, so that gives you 864GB/sec and 1152GB/sec
 
"Alleged"

As pointed out by others, fake.

Main reason being is the weird ROP to memory bus width and capacity. 24 GB is possible on a 4096 bit wide bus in various means (two 4 GB stacks + two 8 GB stacks, four 6 GB stacks etc.) However, AMD has aligned the number of ROPs with memory bus width. With Vega 20, that equated to 64 ROPs which makes sense. 96 ROPs would suggest a 6144 bit wide bus. Similarly a 6144 bit wide bus would make it straight forward to get to 2 TB/s of memory bandwidth. On a 4096 bit wide bus, that'd take 4 Ghz HBM2e which is a bit higher than the 3.6 Ghz effective record for announced HBM2e. However, a more mundane clock of 2.8 Ghz and a 6144 bit width would provide the claimed 2 TB/s bandwidth. Something is horribly amiss.
 
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As pointed out by others, fake.

Main reason being is the weird ROP to memory bus width and capacity. 24 GB is possible on a 4096 bit wide bus in various means (two 4 GB stacks + two 8 GB stacks, four 6 GB stacks etc.) However, AMD has aligned the number of ROPs with memory bus width. With Vega 20, that equated to 64 ROPs which makes sense. 96 ROPs would suggest a 6144 bit wide bus. Similarly a 6144 bit wide bus would make it straight forward to get to 2 TB/s of memory bandwidth. On a 4096 bit wide bus, that'd take 4 Ghz HBM2e which is a bit higher than the 3.6 Ghz effective record for announced HBM2e. However, a more mundane clock of 2.8 Ghz and a 6144 bit width would provide the claimed 2 TB/s bandwidth. Something is horribly amiss.
thanks but youre preaching to the choir
 
As pointed out by others, fake.

Main reason being is the weird ROP to memory bus width and capacity. 24 GB is possible on a 4096 bit wide bus in various means (two 4 GB stacks + two 8 GB stacks, four 6 GB stacks etc.) However, AMD has aligned the number of ROPs with memory bus width. With Vega 20, that equated to 64 ROPs which makes sense. 96 ROPs would suggest a 6144 bit wide bus. Similarly a 6144 bit wide bus would make it straight forward to get to 2 TB/s of memory bandwidth. On a 4096 bit wide bus, that'd take 4 Ghz HBM2e which is a bit higher than the 3.6 Ghz effective record for announced HBM2e. However, a more mundane clock of 2.8 Ghz and a 6144 bit width would provide the claimed 2 TB/s bandwidth. Something is horribly amiss.

I mean I don't disagree that the rumor is fake, but AMD's ROPs have historically NOT been tied to the memory bus width like on nvidia cards. IMO a 96ROP card with an "even number" memory bus width is not implausible.
 
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