Yes. If section of a cmos logic is totally idle then the power consumption is limited to gate and subthreshold drain current.gotcha.....
I guess it helps in idle state. how much? We'll find out soon I suppose.
Under normal usage, the total power of a chip is the sum of the static and dynamic power. Off the top of my head I couldn't tell you what the relative sizes of these two are, but in ideal conditions static power dissipation is low compared to dynamic, meaning that if you cut the frequency in half it roughly drops the power to half.
Power is also proportional to the square of the voltage (in both static and dynamic), so this is a somewhat "faster" way to reduce energy consumption. It also has no effect on processing throughput.