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B3's Samples Recieved

Surprising that AMD let anyone test it.

Last week AMD gave a schedule for ramping and availability: AMD Says Barcelona Bug Is Fixed, Almost Ready to Ramp
But soon, according to Kevin Knox, vice president of AMD's worldwide commercial business (which means servers and workstations), Barcelona and Budapest, which we will know as the Opteron 1000s and the Athlon AM3, are getting back on track. "The bottom line is that the table lookahead buffer errata in the Barcelona chips is fixed in the B3 stepping," says Knox. "It is fixed in silicon and it does not require any BIOS workarounds. More importantly, we are ahead of schedule on the B3 stepping in terms of getting chips to OEM partners and channel partners." Knox says that AMD is ramping up the B3 tweak on Barcelona now using its 65 nanometer processes and will ship "tens of thousands" of parts to OEM and channel customers in late March, and AMD expects the ramp to go quickly enough to have vendors shipping products based on Barcelona in the early part of the second quarter--April, to be specific.
Click to expand...

I read a rumor (take it for what it's worth) that the "B3" stepping code was held steady for more than one stepping. That explains the long delay between the beginning of January when B3 samples came back to now where it's still not ramping/barely starting to ramp.
 
So apart from the TLB bug, it appears nothing else has been improved from B2. The IMC/L3 @ 1.8GHz limitation is still there, as is the low overclocking headroom...

Sucks for those who thought B3 would be some miracle stepping to propel Phenom to, well, phenomenal performance. ;)
 
harpoon said:
So apart from the TLB bug, it appears nothing else has been improved from B2. The IMC/L3 @ 1.8GHz limitation is still there, as is the low overclocking headroom...

Sucks for those who thought B3 would be some miracle stepping to propel Phenom to, well, phenomenal performance. ;)
Click to expand...

Deneb and Shanghai are the best bet for any performance improvements.
 
remember they only cxl'ed the 9700 and 9900 because of the tlb.

so they may just suprise us all with those or something better. <<< wishfull thinking i know. :)
 
peta328 said:
They did mention that they used a Gigabyte 780G board.
Click to expand...

oh i must have missed that part. i do now know after reading through several other forums. unless your on a 790fx with the right bios. you will never be able to get the full potentioal of the phenom. pre-790fx bios's do not have all the settings needed to ht,and nb in check.
 
harpoon said:
So apart from the TLB bug, it appears nothing else has been improved from B2. The IMC/L3 @ 1.8GHz limitation is still there, as is the low overclocking headroom...

Sucks for those who thought B3 would be some miracle stepping to propel Phenom to, well, phenomenal performance. ;)
Click to expand...

That wasn't an uncommon thought. Though I still don't know why anyone would have thought that.

Mr. Bluntman said:
Deneb and Shanghai are the best bet for any performance improvements.
Click to expand...

I wouldn't bet on much there.

SkullCracka said:
remember they only cxl'ed the 9700 and 9900 because of the tlb.

so they may just suprise us all with those or something better. <<< wishfull thinking i know. :)
Click to expand...

Very wishful thinking.

SkullCracka said:
http://www.overclock.co.uk/product/AMD-Phenom-9850-Black-Edition-Quad-Core-AM2+,-Retail_6199.html


hmmm somethings going on. :cool:
Click to expand...

Interesting.
 
SkullCracka said:
oh i must have missed that part. i do now know after reading through several other forums. unless your on a 790fx with the right bios. you will never be able to get the full potentioal of the phenom. pre-790fx bios's do not have all the settings needed to ht,and nb in check.
Click to expand...

Shouldn't the 780g chipset be more correct to over the 790fx due to the latest SB700?

I read the 790fx boards bios are pretty flakey.
 
nas82 said:
Shouldn't the 780g chipset be more correct to over the 790fx due to the latest SB700?

I read the 790fx boards bios are pretty flakey.
Click to expand...

I haven't experienced the 790FX boards as flaky but rather as having a shitty layout and not being able to FSB overclock Phenoms worth a damn.
 
ther is no fsb.

stay away from the msi 790fx. it doesnt have all the options needed either.

its a good board i like msi. but right now its looking like the asus is the best 790fx out.
 
I am wondering if the new DFI Lanparty 790GX M2R is going to be a better choice for stability and overclocking, I believe it uses the 780G + SB700 and has 2 16X PCI-E slots.

cebit_dfi_high_end_05.jpg
 
pxc said:
Surprising that AMD let anyone test it.
Click to expand...

I think it's a good move though. They're basically saying "See? No more TLB bug, no more performance loss because of a workaround! Phenom is okay now".
 
Mr. Bluntman said:
So then what do you make of all the rumors speaking of a 20% IPC improvement going the rounds, Dan?
Click to expand...

Any IPC improvement has to come from differences in the core, that would require a major overhaul, I call shens.
 
Mr. Bluntman said:
So then what do you make of all the rumors speaking of a 20% IPC improvement going the rounds, Dan?
Click to expand...
Link to the site posting the rumor and then we can evaluate the source.

The first impression I get is pure wishful thinking, or someone confusing speed increases as IPC increases (2.3GHz vs 2.8GHz is a 20% increase).
 
j1979 said:
this site says the work around can account for " performance-drop of up-to 40 per cent"


http://www.hexus.net/content/item.php?item=12289

maybe phenom not as shit as first thought
Click to expand...

Except that the reviews and benchmarks that were done at launch were done without the workaround, because AMD didn't officially recognize the problem for desktop CPUs yet.
So the perceived performance at launchtime is the same as the performance of the fixed B3.
 
And AMD backtracked on forcing the fix on desktop board makers. Most boards can disable the fix. I made a thread with a link to Phenom compatible boards, with a column for boards that can disable the TLB fix.

Maybe Mr. Bluntman can clear up what he posted, whether he was talking about B3 (obviously not from the AT benchmarks) or 45nm.
 
pxc said:
And AMD backtracked on forcing the fix on desktop board makers. Most boards can disable the fix. I made a thread with a link to Phenom compatible boards, with a column for boards that can disable the TLB fix.

Maybe Mr. Bluntman can clear up what he posted, whether he was talking about B3 (obviously not from the AT benchmarks) or 45nm.
Click to expand...

I will be more than happy to clear that up for you guys.

The rumors making the rounds pertain to Deneb and Shanghai, saying that they will have a 15-20% IPC improvement over Agena and Barcelona. Weither that's due to the extra 4MB of L3 cache, improved cache latencies, faster NB clocks, the extra HT link, or further tweaks to the actual processing elements remains to be seen.
 
Mr. Bluntman said:
I will be more than happy to clear that up for you guys.

The rumors making the rounds pertain to Deneb and Shanghai, saying that they will have a 15-20% IPC improvement over Agena and Barcelona.
Click to expand...
The point was the source of the rumors. Do you have a link? If it's Theo Valich, don't bother.
 
pxc said:
The point was the source of the rumors. Do you have a link? If it's Theo Valich, don't bother.
Click to expand...

I may as well not bother. To a point. It's a combination of the Inq, Fudzilla, but the last one is from Anandtech. In their CeBit coverage, he says that AMD's partners have got hold of Shanghai samples and did some preliminary benchmarks and were "very pleased" with the performance improvements.

http://it.anandtech.com/IT/showdoc.aspx?i=3261&p=5
 
Mr. Bluntman said:
It's a combination of the Inq, Fudzilla, but the last one is from Anandtech. In their CeBit coverage, he says that AMD's partners have got hold of Shanghai samples and did some preliminary benchmarks and were "very pleased" with the performance improvements.
Click to expand...
Yeah, that's what I figured. One rumor site relying on another, relying on another.

Fuad's "source" is a 2006 slide that has nothing to do with Shanghai (it's a pre-silicon Barcelona slide): http://epscontest2.home.comcast.net/~epscontest2/presentations/06q2_amd_ad/Slide50.JPG

Theinq uses a generic "claimed" (not by AMD) description with the hope that it has something extra: http://www.theinquirer.net/gb/inquirer/news/2008/03/05/amd-shows-45nm

The anandtech article doesn't say what you mention above, it's a mixture reporting and opinion (underlined):
We heard through the grapevine that AMD's Shanghai has already been benchmarked by a few OEM related people. Those people were very pleased with its performance; the improved IPC and 6 MB L3-cache are probably paying off.
Click to expand...

I'm not doubting there are changes in 45nm that improve performance, but i'm very skeptical that IPC has suddenly improved by more than a few percent. There may be some server workloads that show genuine improvement from the catastrophe of a 2MB L3 cache in Barcelona, but those will be the exceptions. Like I said in the other thread, if there aren't real benchmarks out by June/July, then Shanghai probably isn't worth crowing about.
 
pxc said:
Yeah, that's what I figured. One rumor site relying on another, relying on another.

Fuad's "source" is a 2006 slide that has nothing to do with Shanghai (it's a pre-silicon Barcelona slide): http://epscontest2.home.comcast.net/~epscontest2/presentations/06q2_amd_ad/Slide50.JPG

Theinq uses a generic "claimed" (not by AMD) description with the hope that it has something extra: http://www.theinquirer.net/gb/inquirer/news/2008/03/05/amd-shows-45nm

The anandtech article doesn't say what you mention above, it's a mixture reporting and opinion (underlined):

I'm not doubting there are changes in 45nm that improve performance, but i'm very skeptical that IPC has suddenly improved by more than a few percent. There may be some server workloads that show genuine improvement from the catastrophe of a 2MB L3 cache in Barcelona, but those will be the exceptions. Like I said in the other thread, if there aren't real benchmarks out by June/July, then Shanghai probably isn't worth crowing about.
Click to expand...

I doubt though that just a few percent would make the OEMs "very pleased." Anything less isn't worth "crowing about" as you put it. But we shall soon see. I for one am not getting my hopes up anymore, after hearing that Barcelona would see 2.8GHz chips at launch, and full AM2 compatibility. We all know how that turned out. Also, that slide you pointed out has absolutely NOTHING to do with Shanghai.
 
On a side-note, isn't it ironic that AMD now has to increase cache sizes and speeds on a CPU with integrated memorycontroller to try and compete with a CPU that still uses an FSB?
For years the general consensus was "AMD processors don't need big caches, because they have an integrated controller". That era is definitely over...
Makes me wonder what Intel's Nehalem will be doing. Will the integrated controller actually benefit single-socket systems, or is it solely because it enables high-bandwidth NUMA configurations in multi-socket systems?
At least Intel didn't shrink the cache on Nehalem.
 
Scali2 said:
On a side-note, isn't it ironic that AMD now has to increase cache sizes and speeds on a CPU with integrated memorycontroller to try and compete with a CPU that still uses an FSB?
For years the general consensus was "AMD processors don't need big caches, because they have an integrated controller". That era is definitely over...
Makes me wonder what Intel's Nehalem will be doing. Will the integrated controller actually benefit single-socket systems, or is it solely because it enables high-bandwidth NUMA configurations in multi-socket systems?
At least Intel didn't shrink the cache on Nehalem.
Click to expand...

http://www.news.com/8301-10784_3-9780925-7.html
Intel countered AMD in part by including large amounts of cache memory that can keep information readily on hand for processors instead of requiring them to fetch it from main memory. Intel won't drop its cache when it moves to QuickPath, he said, promising glorious results.
"We've made up for (AMD's) better system architecture with superior caching," Gelsinger said. "When we bring those big caches over to Nehalem, wow."
Click to expand...
 
Scali2 said:
On a side-note, isn't it ironic that AMD now has to increase cache sizes and speeds on a CPU with integrated memorycontroller to try and compete with a CPU that still uses an FSB?
For years the general consensus was "AMD processors don't need big caches, because they have an integrated controller". That era is definitely over...
Makes me wonder what Intel's Nehalem will be doing. Will the integrated controller actually benefit single-socket systems, or is it solely because it enables high-bandwidth NUMA configurations in multi-socket systems?
At least Intel didn't shrink the cache on Nehalem.
Click to expand...


Oh very much so.


Atech said:
http://www.news.com/8301-10784_3-9780925-7.html
Click to expand...

Nehalam is a monster.I wonder what AMD will have at its launch to even try to counter ?
 
Scali2 said:
If AMD doesn't run into any more delays, a 45 nm shrink of Phenom, hopefully.
Otherwise, well this B3 Phenom will have to do.
Click to expand...

Isn't the Nehalem launch pulled into Q3 apparently? Who thinks there is the chance that Nehalem could be launched before Deneb/45nm?
 
Scali2 said:
On a side-note, isn't it ironic that AMD now has to increase cache sizes and speeds on a CPU with integrated memorycontroller to try and compete with a CPU that still uses an FSB?
For years the general consensus was "AMD processors don't need big caches, because they have an integrated controller". That era is definitely over...
Makes me wonder what Intel's Nehalem will be doing. Will the integrated controller actually benefit single-socket systems, or is it solely because it enables high-bandwidth NUMA configurations in multi-socket systems?
At least Intel didn't shrink the cache on Nehalem.
Click to expand...

I know, it's Fuad, but it's still an interesting prospect.

harpoon said:
Isn't the Nehalem launch pulled into Q3 apparently? Who thinks there is the chance that Nehalem could be launched before Deneb/45nm?
Click to expand...

If it's pulled into Q3, I bet it will be here before Shanghai.
 
jwlangs said:
I know, it's Fuad, but it's still an interesting prospect.
Click to expand...

Even if this is true, I doubt that a 0 MB L3 cache model will be competitive in terms of performance. It could be the next Sempron or something like that (good bang for the buck, but not exactly the fastest CPU in the lineup).
Logic would dictate that shrinking a Phenom to 45 nm and removing the L3 cache would only affect the IPC in a negative way. They might be able to clock the CPU higher without L3 cache though. But I doubt it'd actually come out faster than the 6 MB model at a lower clockspeed. Clockspeed has never been a good substitute for cache in the past, neither with Intel nor with AMD.
 
Scali2 said:
Even if this is true, I doubt that a 0 MB L3 cache model will be competitive in terms of performance. It could be the next Sempron or something like that (good bang for the buck, but not exactly the fastest CPU in the lineup).
Logic would dictate that shrinking a Phenom to 45 nm and removing the L3 cache would only affect the IPC in a negative way. They might be able to clock the CPU higher without L3 cache though. But I doubt it'd actually come out faster than the 6 MB model at a lower clockspeed. Clockspeed has never been a good substitute for cache in the past, neither with Intel nor with AMD.
Click to expand...

True, cache only helps untill a certain size, after the preformance benefit becomes miniscule
 
"Bug-free" processors are a fantasy. All processors have errata.

It is most important that there are no major unpatched/non-worked around bugs.

The only crummy thing AMD does with errata (and that document shows) is erase any trace of the historical errata. There was an article that looked into this a couple of years ago and AMD basically told the guy he needed to sign an NDA to get the older versions of the errata documents. But AMD relented at the last minute before he published. The documents are still not available to the public on AMD's site.
 
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