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amd_inside
Weaksauce
- Joined
- Jun 27, 2004
- Messages
- 68
Alright, I've heard several things relating to the existance of SSE3 instructions on the D0 core. Some say it's not there, some say it's disabled, others claim it's just not being picked up my programs due to various reasons.
I've come to set the story straight. Tell me which one's correct, please. The D0 Winchester core:
- has no trace of SSE3 instructions. That's reserved for the E0 core. The Winchester is simply a die shrink and nothing more (with maybe the exception of a few bug fixes)
- has the SSE3 set, but it's disabled/broken. AMD has disabled this instruction set for instability reasons.
- has them enabled, but they're just not being found by programs. It's simply a matter of redirecting the application.
Thanks!
I've come to set the story straight. Tell me which one's correct, please. The D0 Winchester core:
- has no trace of SSE3 instructions. That's reserved for the E0 core. The Winchester is simply a die shrink and nothing more (with maybe the exception of a few bug fixes)
- has the SSE3 set, but it's disabled/broken. AMD has disabled this instruction set for instability reasons.
- has them enabled, but they're just not being found by programs. It's simply a matter of redirecting the application.
Thanks!