AMD's Infinity Fabric vs Intel's Ring Bus

[_mockingbird]

Would someone with advance understanding explain to me how does AMD's Infinity Fabric compare to Intel's Ring Bus?

 

[sirmonkey1985]

easiest way to explain infinity fabric is to go read up about hypertransport, it's the same basic concept. as far as ring bus goes i haven't bothered to really read into it much but i think toms hardware did an in depth explanation of ring bus on their 7900x review.

 

[_mockingbird]

easiest way to explain infinity fabric is to go read up about hypertransport, it's the same basic concept. as far as ring bus goes i haven't bothered to really read into it much but i think toms hardware did an in depth explanation of ring bus on their 7900x review.

Are they basically different implementations of the same thing?

 

[sirmonkey1985]

Are they basically different implementations of the same thing?

for infinity fabric pretty much, HT was cpu to cpu and cpu to chipset while infinity fabric does CCX to CCX and die to die.. hypertransport was replaced by using pcie 3.0 lanes.

if you're talking about ring bus, they're quite different implementations and both have their weaknesses and strengths. which one is the correct way only time will tell but i have a feeling intel's reached the limits of their current architecture.

 

[_mockingbird]

for infinity fabric pretty much, HT was cpu to cpu and cpu to chipset while infinity fabric does CCX to CCX and die to die.. hypertransport was replaced by using pcie 3.0 lanes.

if you're talking about ring bus, they're quite different implementations and both have their weaknesses and strengths. which one is the correct way only time will tell but i have a feeling intel's reached the limits of their current architecture.

Intel did introduced Mesh Architecture in Skylake-X

 

[CombatChrisNC]

I don't know if it's ever been discussed together, but I wanted to link them.

PCIe 4 is coming. Zen+ is coming. Will Zen+ use PCIe 4 speeds with it's infinity fabric? Same number of lanes, just higher speed?

 

[AlexisRO]

A good read/ vid on the matter here and here.

 

[ecmaster76]

I was going to compare the two approaches and then it struck me I have no clue where Intel plumbed in the L3 on the new mesh interconnect . Turns out each core has its own little 1.375 MB L3

So Intel connects the mesh to each core's L3 such that any core is only a few hops away from another for very consistent latency. External access is handled by separate Memory Controller, QPI (other CPU sockets), etc. are "cores" that are essentially peers on the mesh network.

AMD connects 4 cores to a common L3 ( this unit is called a CCX) and then that is connected to the IF. Latency varies depending on whether or not another core is on the same CCX. The IF connects to other CPU sockets, the memory controller and other uncore functionality. It also functions as the PCIe controller. The biggest win is that latency from one CCX to another isn't a huge jump if they aren't on the same socket since its the same interconnect either way. They can also bolt on integrated graphics as well since its part of Vega.

 

[Shintai]

Infinity Fabric and ringbus as such got nothing in common. The equal to infinity fabric is QPI or UPI. Also why a single Epyc CPU on package got worse latencies than a 4 socket UPI Xeon.