AMD Strix Point Silicon Pictured and Annotated

[erek]

"Slightly separated from the iGPU are its allied components, the Media Engine, and the Display Engine. The Media Engine provides hardware acceleration for encoding and decoding of h.264, h.265, and AV1, besides several legacy video formats. The Display Engine is responsible for encoding the frame output of the iGPU to the various connector formats (such as DisplayPort, eDP, HDMI), including hardware-accelerated display stream compression; while the display PHYs handle the physical layer of the connectors.

The NPU is the third major logic component of "Strix Point." This second generation NPU by AMD is visibly larger than the one found in "Phoenix." It is based on the more advanced XDNA 2 architecture, and contains 32 AI engine tiles, talking to its own high-speed local memory, and a control logic that interfaces with Infinity Fabric. This NPU is designed to meet and exceed the hardware requirements of Microsoft Copilot+, and provides a throughput of 50 TOPS.

The memory controller supports dual-channel (160-bit) DDR5 with native DDR5-5600; and 128-bit LPDDR5 at speeds of up to LPDDR5-7500. The controller features an unspecified size of SRAM cache, which Nemez notes was also seen on the "Phoenix 2" and "Phoenix" dies, but not on the memory controller of the cIOD found in "Raphael" and "Dragon Range."

The "Strix Point" silicon has a smaller PCIe root complex than "Phoenix," which in turn has a smaller root complex than "Cezanne." AMD has been reducing the PCIe lane count by 4 over the past three generations. "Cezanne" features 24 PCIe Gen 3 lanes (x16 PEG + x4 NVMe + x4 chipset bus or GPP); while "Phoenix" truncates this to 20 PCIe Gen 4 lanes (x8 PEG + x4 NVMe + x4 chipset bus or GPP + x4 configured as USB4). The newer "Strix Point" cuts it down further to just 16 PCIe Gen 4 lanes (x8 PEG + x4 NVMe + x4 configured as USB4 or GPP).

The idea behind the PCIe lane reduction is that "Strix Point" is designed to square off against "Lunar Lake," which too only has x4 for PEG/GPP, and when "Arrow Lake-H" and "Arrow Lake-HX" eventually hit the scene, they'll be met with AMD's "Fire Range" chip that has a 28-lane PCIe Gen 5 interface and can be paired with even the fastest discrete mobile GPUs."

Source: https://www.techpowerup.com/325035/amd-strix-point-silicon-pictured-and-annotated

 

[Marees]

Apparently since strix point has the p & c cores in different ccx (with diff cache ratios) it results in performance issues in some scenarios

Upcoming kraken point with 4p + 4c & half the igpu all hopefully packaged together should give better performance in certain single threaded scenarios (dgpu gaming or igpu low power gaming in handhelds)

 

[1337Goat]

WOW what in the world!? Now I have never seen a modern CPU LABELED like that before! That is really really cool to see.
AMD, you are for sure doing some great stuff. Please defeat Nvidia and become the new Lords of AI and VRAM!!!

 

[Marees]

Don’t expect AMD RDNA 3.5 handhelds or mini PCs for a while​

According to mini PC manufacturer Aoostar, Ryzen AI 300 series processors won’t be available “until October at the earliest.” Strangely, it claims that it already has compatible motherboards but hasn’t received CPUs from AMD for testing. This is according to ‘AOOSTAR-Liang’, a moderator of the company’s Discord (via Videocardz).

Whatever AMD has planned, it better act fast. Intel already has a Lunar Lake handheld en route in the form of MSI Claw 8 AI Plus, presumably soon. It’s safe to assume most manufacturers will opt for Ryzen APUs, but it’s never wise to rest on one’s laurels.

https://www.club386.com/dont-expect-amd-rdna-3-5-handhelds-or-mini-pcs-for-a-while/