Emission
Supreme [H]ardness
- Joined
- Dec 6, 2005
- Messages
- 4,420
By the interconnect ability and bandwidth. Just as seen on Ryzen between CCXes. Now scale up, take a 2S system with 8 dies in total. Each die got 2 GMI links and tell me how many hops and shared bandwidth links you need instead of direct.
I could be wrong, but it sounds like you're oversimplifying the complexity of the implementation, especially considering how we don't have much data to go on yet about real world performance.