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I have a really huge question here will we see the steamroller core in the am3+ form factor?
I ask this since the roadmap for 28nm cpu/apu AM3+ is essentially dead. If that is the case will amd release a full 8 core Steamroller FX APU?
Someone linked this in the other thread:
http://www.pcper.com/reviews/Editor...nd-New-Design-Philosophy-Dictates-Faster-Pace
I highly recommend you read it. It should answer some of your questions.
From everything I've read up to now, it is pointing towards a new socket. Some sites say G34 or C32 sockets from their server processors or a new AM4 socket. I don't know about an FM3 socket ever being mentioned.
If going by PCPer's article, AMD is moving towards getting their APU from mobile to entry/mid-range desktop to eventually high-end/enthusiast and server use. The next APU, Kaveri, after Trinity will have a GCN-based GPU on the same die as the CPU.
Imagine an AMD FX processor in 2013 or 2014 with improved Piledriver modules paired with the next generation GCN cores from their GPU products. And, imagine an AMD Opteron CPU based around that as well. That's where AMD is headed.
And, with all intents and purposes, it looks like they will use an entirely new socket.
Someone linked this in the other thread:
http://www.pcper.com/reviews/Editor...nd-New-Design-Philosophy-Dictates-Faster-Pace
I highly recommend you read it. It should answer some of your questions.
From everything I've read up to now, it is pointing towards a new socket. Some sites say G34 or C32 sockets from their server processors or a new AM4 socket. I don't know about an FM3 socket ever being mentioned.
If going by PCPer's article, AMD is moving towards getting their APU from mobile to entry/mid-range desktop to eventually high-end/enthusiast and server use. The next APU, Kaveri, after Trinity will have a GCN-based GPU on the same die as the CPU.
Imagine an AMD FX processor in 2013 or 2014 with improved Piledriver modules paired with the next generation GCN cores from their GPU products. And, imagine an AMD Opteron CPU based around that as well. That's where AMD is headed.
And, with all intents and purposes, it looks like they will use an entirely new socket.
Read that somewhere too but are AMD far enough ahead to make their main desktop APU into something which works well enough for the current market (cpu).
Or does it mean a larger design, which would mean worse yields...
If Steamroller is such a product what would be it's target audience?
It's unlikely to be much larger. The 28nm production will be bulk and probably TSMC/GloFo and they generally have very good transistor density for a given node (or half node in this case). If they do an all-APU lineup then they could potentially decrease the amount of cache thus lowering the size even more. The Bulldozer chips were big partially because of the excess amounts of L3 and L2 cache and this was mainly due to it being a server chip -- that much slow cache is unnecessary on the desktop. Decreasing the cache size (hopefully the L2 per module) and going bulk should help. Bear in mind that they'd still be behind Intel who's already sitting on 22nm
It isn't the first time AMD has gone bulk for a CPU/APU either. Brazos was made at TSMC's 40nm
That all sounds nice in theory but look at what happened to Bulldozer, we still haven't heard what exactly went wrong on the production process. If Steamroller runs into the same problems with the die shrink and not enough yields or fast enough for consumers it is another sinking ship.
Read that somewhere too but are AMD far enough ahead to make their main desktop APU into something which works well enough for the current market (cpu).
Or does it mean a larger design, which would mean worse yields...
If Steamroller is such a product what would be it's target audience?
Source.The heterogeneous processor market, also known as the hybrid processor market, is reckoned to be worth $55.5 billion and has particular relevance in such areas as cloud-based data management, streaming, and security.
Source.Hyper Transport is gone as an external interconnect, leaving only PCIe for off-chip IO. The Fusion Control Link is a 128-bit (each direction) interface giving off-chip IO devices access to system memory. Trinity also features a 256-bit (in each direction, per memory channel) Radeon Memory Bus (RMB) direct access to the DRAM controllers. The excessive width of this bus likely implies that it's also used for CPU/GPU communication as well.
IOMMU v2 is also supported by Trinity, giving supported discrete GPUs (e.g. Tahiti) access to the CPU's virtual memory. In Llano, you used to take data from disk, copy it to memory, then copy it from the CPU's address space to pinned memory that's accessible by the GPU, then the GPU gets it and brings it into its frame buffer. By having access to the CPU's virtual address space now the data goes from disk, to memory, then directly to the GPU's memoryyou skip that intermediate mem to mem copy. Eventually we'll get to the point where there's truly one unified address space, but steps like these are what will get us there.
AMD won't be able to use their APUs for HPC purposes until they fix their bus width issues.
This thread is worth a read, if only for 2-3 pages of it and disregarding the AVX2 talk.
My post (pelov) shows the pictures and the architectural issues AMD has to deal with in seeing their HSA agenda becoming free of potential bottleneck issues that they're already facing. Given current implementations, there isn't much to hope for in Trinity for HPC other than for low-grade tasks where you could save money and avoid Teslas+Xeons. Remember that bus width, GDDR5 (ECC version) and perf-per-watt and cost are what govern the sales and success for HPC products. Trinity still relies on DDR3 at 1866 where it's already bottlenecked by an onion and garlic bus width. It isn't wide nor fast enough for HPC tasks.