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Agena & Kuma Details

M

Metr0

n00b
Joined
Jul 17, 2006
Messages
35
Core Enchancements:

128 Bit floating point:
  • Applies only to Agena & Kuma

New SSE4A instructions:
  • Advanced Bit manipulation
  • MWAIT & MONITOR instructions
  • Misaligned SSE Mode
Additional Features:
  • Power management state invariant time stamp counter (TSC)
  • increased number of TLB Page entries
  • 1GB large paging support
  • Physical address space increased to 48 bits
IMC Enhancements

DDR2 Dimms in products variations:
  • Socket AM2+: Dual Channel unbuffered 1066 support
  • Socket 1207+ Dual Channel unbuffered 1066 support
Memory Controller enhancements
  • Write Burst & DRAM prefetching performance improovements
  • DRAM writes can be buffered in the memory controller before being opportunistically bursted into DRAM controler to improve DRAM interface efficiency
  • Read prefetcher detects stride paterns and issues prefetch requests based on confidence level
  • Channel Interleaving
Roadmap:

Agena FX:

Q3 2007:
2.7-2.9GHz
2MB L2 total L2 cache for the CPU (quad core so 512KB each core)
2MB shared L3
Socket 1207+
4000MHz hypertransport Bus
TDP not determined yet
65nm SOI

Agena:

Q3 2007:
2.4-2.6GHz
2MB L2 total L2 cache for the CPU (quad core so 512KB each core)
2MB shared L3
Socket AM2+
4000MHz hypertransport Bus
TDP 125W
65nm SOI

Kuma:

Q3 2007:
2.0-2.9GHz
1MB L2 total L2 cache for the CPU (dual core so 512KB each core)
2MB shared L3
Socket AM2+
4000MHz hypertransport Bus
TDP 89w - 65w
65nm SOI


Source Chilehardware
 
nice info thanks........looks promising.......but the link in the original thread gives me a 404 error though........
 
the enhancements seem OK...but would like to see real world benchmarks b4 being AMDs bitch again :p and we're still a long time away from Q3 2007 :\
 
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