4.2C Vs. 4.2E Who will win?

Yes interesting, but they forgot to mention that shortly after the benchmark suite with Prescott was completed, the caps and mosfets on the motherboard performed what appeared to be an explosion in the form of a small mushroom cloud, approximately 5ft. tall :p
 
Originally posted by PliotronX
Yes interesting, but they forgot to mention that shortly after the benchmark suite with Prescott was completed, the caps and mosfets on the motherboard performed what appeared to be an explosion in the form of a small mushroom cloud, approximately 5ft. tall :p
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:rolleyes:
 
That's interesting. Certainly sobering considering all the info we've been fed about Prescott over 4 ghz.
 
Prescott scaled a little better than Northwood. But Galatin(EE) scaled even better that Prescott.

Its all about the cache.

The larger cache operating at faster frequecies makes it scale higher.

Nothing impressive about it.

Most benchmarks stayed the same across the frequencies.
 
Wow, the Prescott didn't seem to gain a lead over the Northwood like Anand thought would happen at 3.6 GHz. The results seemed proportionally similar at 4.2 GHz as they did at 3.2 GHz. Pretty disappointing if you ask me...
 
very sad for precott
i feel bad for people "upgrading" or should I say downgrading :rolleyes:
 
Originally posted by xonik
Wow, the Prescott didn't seem to gain a lead over the Northwood like Anand thought would happen at 3.6 GHz. The results seemed proportionally similar at 4.2 GHz as they did at 3.2 GHz. Pretty disappointing if you ask me...
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yes and in other news, Anand likes to spew FUD.
 
Originally posted by pakotlar
yes and in other news, Anand likes to spew FUD.
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damn responsible internet hardware sites and their good reputations
 
Originally posted by Kirkov
very sad for precott
i feel bad for people "upgrading" or should I say downgrading :rolleyes:
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its only by a fraction, but yeah the heat issue sux too.. prescott is teh flop.. owell im sure my northwood will hold me of till tejas.
 
I was thinking about this in the shower this morning...

Thanks
 
Looks like more evidence that Prescott can stay in the grill with the other pieces of charcoal for now and the Northwoods are still the way to go. That is unless Intel figures out a better FAB process for Prescott.
 
Originally posted by EnderW
Does anyone think the new socket will change anything?
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It can help b/c they can spread out the power intake, which should decrease the leakage. Closer grounding, etc.

I'm still trying to figure out what they are doing with the extra almost 300 pins? Seems a bit much when last time they added pins it only went from 370 to 423 then 423 to 478.

P4 = 478 --- Athlon XP = 462
new = 775 --- A64=754

Maybe they are adding an integrated memory controller?! LOL
Nah, at least not yet.
 
The leakage is at the transistor level. A new physical interface won't decrease current leakage in any capacity. The socket is for increased current handling, made necessary by increased current draw.
 
Originally posted by xonik
The leakage is at the transistor level. A new physical interface won't decrease current leakage in any capacity. The socket is for increased current handling, made necessary by increased current draw.
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Yes, but if the current can be supplied closer to where it is needed it will not have to travel across as many transistors. So few transistors to travel over = less leakage. understand?

Also it should allow a higher FSB.

Similar to how an 8 layer chips clocks higher than a 6 layer interconnect chip.
 
Originally posted by chrisf6969
Yes, but if the current can be supplied closer to where it is needed it will not have to travel across as many transistors. So few transistors to travel over = less leakage.
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No, that's totally wrong. The leakage happens because at 90 nanometers, the transistors are so close together that the dielectric material separating them becomes less effective at isolating the flow of charge through transistors. Since the Prescott and other future 90 nanometer processors will feature more transistors, more closely spaced, the problem of current leakage will intensify unless improved dielectric solutions like silicon-on-insulator or a low-k germanium or silicon is used.
 
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