>1 divider, meaningful?

[CoW]8(0)]

Is having a memory divider that's >1 at all meaningful?

For example:
FSB = 400Mhz (1600Mhz quad pumped)
Memory Divider = 3:2

Therefore, the memory would be running at 1200Mhz.

But is so much bandwidth ever useful? Since the FSB is transferring data at 800Mhz for DDR2, the data should never be moved between RAM and CPU faster than 800Mhz.

By this reasoning, there would be no performance difference between running the RAM at 800Mhz (1:1 divider) as opposed to 1200Mhz.

Is this logically correct?

 

[SLee]

There is a difference, assuming the C2D is clocked at the same speed, faster memory will improve performance (slightly):

http://www.xbitlabs.com/articles/memory/display/core2duo-memory-guide_4.html#sect0

 

[CoW]8(0)]

This poor performance of fast DDR2 SDRAM is due to the architecture of Core 2 Duo systems in which memory is connected to the CPU via the chipset and two sequential buses. In this design it is not the bandwidth of dual-channel high-frequency memory that becomes the bottleneck, but the Quad Pumped Bus that connects the CPU with the chipset's North Bridge. Its maximum theoretical bandwidth is 8.5GB/s in Core 2 Duo systems, which only equals the bandwidth of dual-channel DDR2-533 SDRAM. That's why we don't see a really big performance growth if we use memory faster than DDR2-533.

But I don't see why there's any performance growth going to faster memory.

 

[SLee]

Even if the FSB is a bottleneck, increasing memory speeds helps reduce the latency between the memory controller and the RAM.