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    Forwarding control outputs for pipeline stages of given MIPS assembly

    I've just finished trying this problem from my book but there's no answer key and I'm not fully sure and would like to know if I've done it correctly, or am overlooking something. I'm assuming MUX is for determining the rt value and the other rs? Is that correct?
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    MIPS Assembly stalls and forwarding when a register's value isn't modified in previous step

    I'm going over pipelining and stalls and forwards with MIPS architecture, and there's a couple things I'm uncertain about. If two adjacent instructions, such as the first two of each set bellow, both use the same register, but the first isn't actually modifying that register, is there still a...
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    MIPS Assembly to C++ convert

    I am doing book problem that wants translated MIPS assembly to matching C++ lines. it gives: k = $s0, A[] base address = $s7 addi $t0, $s7, 4 add #t1, $s7, $0 sw $t1, 0($t0) lw $t0, 0($t0) add $s0, $t1, $t0 my attempt to solve what it doing: t0 = &A[1] t1 = &A[0] 0(t0)/A[1] = &A[0] ?? t0 =...