1. cageymaru

    TSMC Announces 6-nanometer Process

    TSMC has announced its new 6nm process node that delivers 18% higher logic density over the N7 process while maintaining design rules from TSMC's proven N7 technology. This allows customers to fully migrate over to the new node with a fast design cycle time while reusing the N7 design...
  2. cageymaru

    Samsung Announces 5nm EUV Development Milestone

    Samsung has announced that its 5nm FinFet process technology is complete in its development and is ready for customer sampling. Compared to 7nm, Samsung’s 5nm FinFET process technology provides up to a 25% increase in logic area efficiency with 20% lower power consumption or 10% higher...