Samsung Announces 5nm EUV Development Milestone

cageymaru

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Samsung has announced that its 5nm FinFet process technology is complete in its development and is ready for customer sampling. Compared to 7nm, Samsung’s 5nm FinFET process technology provides up to a 25% increase in logic area efficiency with 20% lower power consumption or 10% higher performance as a result of process improvement to enable the advanced foundry to have a more innovative standard cell architecture. The 5nm EUV lithography process reduces mask layers while providing better fidelity.

Samsung partners who have adopted its 7nm process can easily migrate to the 5nm node as all of the 7nm intellectual property (IP) applies to 5nm. Thereby 7nm customers transitioning to 5nm will greatly benefit from reduced migration costs, pre-verified design ecosystem, and consequently shorten their 5nm product development. The process design kit (PDK) has been available since Q42018 and Samsung Foundry has already started offering 5nm Multi Project Wafer (MPW) service to customers. Samsung is collaborating with its customers on a customized 6nm process node with EUV lithography technology. The first 6nm chips have already been tape-out and the company has announced that it is expanding its Korean production lines for the advanced nodes.

“In successful completion of our 5nm development, we’ve proven our capabilities in EUV-based nodes,” said Charlie Bae, Executive Vice President of Foundry Business at Samsung Electronics. “In response to customers’ surging demand for advanced process technologies to differentiate their next-generation products, we continue our commitment to accelerating the volume production of EUV-based technologies.” “Considering the various benefits including PPA and IP, Samsung’s EUV-based advanced nodes are expected to be in high demand for new and innovative applications such as 5G, artificial intelligence (AI), high performance computing (HPC), and automotive. Leveraging our robust technology competitiveness including our leadership in EUV lithography, Samsung will continue to deliver the most advanced technologies and solutions to customers.”

Current Samsung facilities.

Current-Hwaseong-EUV-Line-as-of-March-2019.jpg


Expected expansion.

Expected-aerial-view-of-Hwaseong-EUV-Line.jpg
 
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lostin3d

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Amazing how it dwarfs most of the nearby buildings and appears to occupy around a 1/3 of the entire city.
 

GoodBoy

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Are all those cookie cutter high rises the apartments that the workers live in?
 

Zarathustra[H]

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Seeing how fast Samsung is moving on from 7nm to 5nm, it is even more surprising how much trouble Intel, the king of the silicon fab process has had with 10nm.

That said, these process node numbers don't mean shit anymore. Samsungs 5nm is equivalent to - what - approximately what we would have called 8nm in the past?
 

GoodBoy

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By the time you get down to 2nm, the quantum effects are so large that these transistors will not function like they do now.

So after 5nm, there's maybe 1 or 2 more shrinks.

Moore's law died around 2008.
 

Zarathustra[H]

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By the time you get down to 2nm, the quantum effects are so large that these transistors will not function like they do now.

So after 5nm, there's maybe 1 or 2 more shrinks.

Moore's law died around 2008.
Well, technically Moore's law really only speaks to transistor count, and in that regard, with added core count and larger caches, the transistor count is still roughly doubling every two years. It's not exact, but its not that far off either.
 

GoodBoy

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I did the math based on a wiki page for the nvidia gpus from the last 20 ish years. Remember, it is a doubling per area X, not the area increasing or total count in a processor, that is specified in Moore's Law. Doubling (count per area) every 2 years last happened in 2008. There has been a few doublings since 2008, but not at the pace that Moore Law specified. We got a few more shrinks to go, and then something totally new will have to happen.. But Moore's law is already dead.

Duo-tronic is next I think, followed by Positronic in a few hundred years.
 

Zarathustra[H]

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I did the math based on a wiki page for the nvidia gpus from the last 20 ish years. Remember, it is a doubling per area X, not the area increasing or total count in a processor, that is specified in Moore's Law. Doubling (count per area) every 2 years last happened in 2008. There has been a few doublings since 2008, but not at the pace that Moore Law specified. We got a few more shrinks to go, and then something totally new will have to happen.. But Moore's law is already dead.

Duo-tronic is next I think, followed by Positronic in a few hundred years.

I've never heard it defined that way. I've always heard it defined as a doubling of the total number of transistors in a dense circuit (like a CPU) every two years.
 

DejaWiz

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I've never heard it defined that way. I've always heard it defined as a doubling of the total number of transistors in a dense circuit (like a CPU) every two years.
Yep. Moore never defined it as transistor count doubling in the same area/dimensions of the IC.
 
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N4CR

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Raja put some weight on at Intel. Or it was all that sabbatical Indian food ;)
 

whateverer

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Yep. Moore never defined it as transistor count doubling in the same area/dimensions.
Right, it's always been about "twice the productivity the same price", after one-time costs. You can do that by increasing your wafer size from 4" to 6", or by automating/optimizing more stages in your fab line....or optical shrink, or changing your process type (to up yields). You had lots of options back when the industry was still new, and most things were done by hand.

These monster fabs exist because our appetite for semiconductors has grown monstrous. You can't hope to make a dent in demand without building big.
 
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