RTX 5090 FE Molten 12VHPWR

Wouldn't the goal not be perfectly balancing the load across all pins, but rather allowing the GPU to cap the amperage draw on pins and lower over all power draw / throw an error once thresholds are reached?
 
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I have a feeling, not backed by hard evidence (of course), that my 5090's connector with imbalanced pins didn't melt (prior to me finding the problem with a WireView 2 Pro) in large part because I've got four 180mm fans blowing in from the side. Airflow from the main opening side of the case is getting quite rare these days, with case manufacturers focusing on the looks of acrylic and glass sides. I don't doubt that the imbalance would have become worse with time and heating/cooling cycles, and would have eventually melted.

Pure speculation on my part since I threw that OEM adapter away and I wouldn't have used it to the point of failure anyways.
do you by any chance have the actual numbers for the amps in each wire when you had a large imbalance?
 
do you by any chance have the actual numbers for the amps in each wire when you had a large imbalance?
The lowest draw was 6.4A, the highest was around 10.6A. I don't have a record of the others (mostly from 7.8 to 8.8, I think), and reseating the connections didn't change them. EDIT - and I don't think there's a way to download the logged data that is located on the WireView Pro 2. EDIT to the EDIT - there is, I'm looking to see if it goes back that many months.
 
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Wouldn't the goal not be perfectly balancing the load across all pins, but rather allowing the GPU to cap the amperage draw on certain pins and lower over all power draw / throw an error once thresholds are reached?
id argue ideally you want it to calculate power dissipated by each pin and set some cap. so measure the voltage drop and current through each pin. that could be kind of difficult, so probably easier to just do what tsumi recommended: measure voltage drop, and once there is enough variation shutdown the system. ofcourse you still haven't fixed the issue, now you have a gpu that randomly shuts off under load.

edit: err, sorry, not voltage drop, measure voltage on the gpu after it comes in from the pin. each one individually.
 
Your end goal is current balancing. Im asking "why"? What do you want to achieve with balanced current? You want to force large amounts of current through connectors that have more resistance than other?
Is it purely the single datasheet spec you are trying to hit?
I'm not trying to force large currents through any particular contact, I'm forcing the current in each contact to be within spec so the connector doesn't burn up. Keep in mind that we have simplified the problem here. The overall current through all of the pins also has to be regulated to a design maximum - this can be done by the power regulator on the board and indeed this is what is happening when the card downclocks on the power limit.

Hitting datasheet specs is engineering. Datasheets are legal documents. Companies that publish them spend a lot of money and expertise to ensure they are correct as if the product is shown not to meet datasheet specs they can and have been sued for big money.

If you don't abide by a datasheet, you are in no man's land and have very little way of bounding any issue that comes up. It could work today, and fail tomorrow, for no obvious reason and no warning.

As a side note on datasheets, one of the skills of oil and gas down hole electronics is the operating temperatures down there are 200C+. Nobody specs electronic components for that, so those guys have to do a lot of characterization because they are on their own.


The resistance values are examples. I dont know the actual variation. I believe 10mohm is nominal. All the datasheets im finding are very sparse on any more detail than that (which gives me very little confidence in the datasheet).

Irritating isn't it? Datasheets are being enshittified too. We are a long way from the days of data books from the likes of National Semiconductor. Connector and switch datasheets tend to be really poor.

Older stuff is spec'ed better. Maybe look up the PCIe 6 and 8 pin connectors and see what those contact resistances are.

You are trying to show me examples of current balancing that work better than non current balanced. But you've introduced an extra variable into your example that I can't isolate away. This example doesn't work.
I just think it may be worth extending your understanding to what these connectors have been hooked to on the PCB for the Pascal series of cards and how that is different for the 5090.
 
If you really want to learn what is going on, get yourself a cheap clamp on meter than can measure DC current. DC current is really important as a lot of clamp meters only measure AC current. Also make sure it has max/min or a peak hold function.

Not an endorsement, but this looks decent at $36: AstroAI Digital Clamp Meter Multimeter 4000 Counts Auto-ranging Amp Tester Measuring AC/DC Voltage & Current, Resistance, Capacitance, Frequency, Continuity, Live Wire Test, NCV Detection, Blue

You can clamp this around all the power wires to get the total current and individual wires to get the individual currents. Turn on the peak hold, run a benchmark and get the peak current.
 
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Wouldn't the goal not be perfectly balancing the load across all pins, but rather allowing the GPU to cap the amperage draw on pins and lower over all power draw / throw an error once thresholds are reached?
Xactly.

Historically the cards would downclock to reduce power when too much current is being drawn or the board is too hot. Eventually the card would stop functioning well at all and may shutdown. Plus they have fuses too.

I know on my Titan Xp, if the second 6 pin PCIe connector is not plugged in, the driver for it will not load in windows. No driver, no 3D, and likely enough power is supplied just from the PCIe motherboard connector to operate in this limp mode state.
 
I'm not trying to force large currents through any particular contact, I'm forcing the current in each contact to be within spec so the connector doesn't burn up.
If multiple parallel wires have large current imbalances, then that means the resistances of the wires are already imbalanced. trying to then force equal currents on every wire is forcing currents through wires that have large resistances. you can already throw out the datasheet, you are already not within specs (even if that particular spec is not printed in the datasheet). current balancing will not save you. if the wires have relatively matched resistances, then you never had a problem to begin with. what is current balancing winning for you here?

Hitting datasheet specs is engineering. Datasheets are legal documents. Companies that publish them spend a lot of money and expertise to ensure they are correct as if the product is shown not to meet datasheet specs they can and have been sued for big money.
I agree you should try to be below max values in a data sheet. however in my experience datasheets often miss out other specs that you are not aware of. How does the connector behave running near the max? How does the actual resistance of each contact interact with out design? What is the temperature derating curve?
 
do you by any chance have the actual numbers for the amps in each wire when you had a large imbalance?
Wow, so it actually saves a TON of samples into chunks. This is the earliest saved chunk - I got tired of looking at idle samples after 50 or so. Separate from this sample log, Pin 2 was the lowest at 6.4 when I was looking at the Thermal Grizzly monitoring program, and pin 6 at 10.6 was the highest. This looks like it's a readout from where I capped power draw at around 80%

7.4​
5.4​
6.7​
6.3​
6.6​
7.8​
7.2​
5.5​
6.9​
5.7​
5.9​
7.6​
7.2​
5.6​
7.3​
5.8​
6.7​
8.3​
7.3​
5.6​
6.9​
5.8​
6.2​
7.9​
7.5​
5.7​
7.3​
5.5​
6.2​
8.4​
7.1​
5.3​
7.5​
5.6​
6.7​
8.4​
7.2​
5.5​
7.1​
5.6​
6.4​
8.3​
6.7​
5.5​
7.3​
5.8​
6.6​
8.5​
7.2​
5.6​
7.1​
5.7​
6.5​
8.2​
2.1​
1.6​
2.3​
1.8​
1.9​
2.4​
 
Wow, so it actually saves a TON of samples into chunks. This is the earliest saved chunk - I got tired of looking at idle samples after 50 or so. Separate from this sample log, Pin 2 was the lowest at 6.4 when I was looking at the Thermal Grizzly monitoring program, and pin 6 at 10.6 was the highest. This looks like it's a readout from where I capped power draw at around 80%

​
so i was just trying to get an idea of typical voltage drop and resistances. just using the top line of your data and assuming your gpu was using 600w * 80% = 480w. I did this kind of backwards, guess at voltage drop, see if the power matches the target, repeat until close enough.
1792168640161.png

i'd say your connector doesnt look too bad, but these are very rough estimates. pin2 resistance might be a little too high, not sure.
 
so i was just trying to get an idea of typical voltage drop and resistances. just using the top line of your data and assuming your gpu was using 600w * 80% = 480w. I did this kind of backwards, guess at voltage drop, see if the power matches the target, repeat until close enough.
View attachment 831525
i'd say your connector doesnt look too bad, but these are very rough estimates. pin2 resistance might be a little too high, not sure.
12.1V per pin under load, if that helps.
 
If multiple parallel wires have large current imbalances, then that means the resistances of the wires are already imbalanced. trying to then force equal currents on every wire is forcing currents through wires that have large resistances. you can already throw out the datasheet, you are already not within specs
Current balancing assumes the connector is of good enough quality that the resistance imbalance is bounded so that the currents and "additional power loss" remain reasonable. It cannot makeup for a fundamentally underspec'ed connector.

Another thing too, is we are not really forcing "equal" currents through them, we are forcing currents to remain inside the connector spec - they can still be different pin to pin.
 
12.1V per pin under load, if that helps.
Yeah it might make the data a little better, but it's already a pretty rough estimate just to get us thinking about some of the values, so I'm not going to pretend that I have the precision to really warrant redoing the calculations.
 

NVIDIA RTX 5090 Gets Quad 8-Pin Power Connector Mod To Bypass Melting-Prone 12V-2×6, Nearly Halves Current Per Wire​

Sebastian Castellanos Oct 16, 2026 at 07:31am EDT

A Modder Has Developed A Quad 8-Pin PCIe Power Connector Conversion For NVIDIA's RTX 5090, Promising Significantly Lower Currents And Temperatures Than The Standard 16-Pin Connector​


https://wccftech.com/nvidia-rtx-509...prone-12v-2x6-nearly-halves-current-per-wire/
Now that's what I'm talking about. Looks pretty elegant too. Much nicer than the pigtails we have seen.

I think we have just seen the 5090's future.
 
Current balancing assumes the connector is of good enough quality that the resistance imbalance is bounded so that the currents and "additional power loss" remain reasonable. It cannot makeup for a fundamentally underspec'ed connector.
If the connector is good enough quality, you don't need to current balance to begin with.
Another thing too, is we are not really forcing "equal" currents through them, we are forcing currents to remain inside the connector spec - they can still be different pin to pin.
You lost me a little here. To clarify, you want the GPU to have an upper limit for the current on each pin, but otherwise let them be if they are below that limit? I'll have to think about that one. (Also wish you clarified this earlier)
 
If the connector is good enough quality, you don't need to current balance to begin with.
Sure. Clearly the current one isn't good enough for that.

Better connector means more $$$ or more size or both.
To clarify, you want the GPU to have an upper limit for the current on each pin, but otherwise let them be if they are below that limit? I'll have to think about that one. (Also wish you clarified this earlier)
Exactly!

I think somethings the wording here balls things up, as the term load balancing implies "equal", but it really does not. The don't have to be equal as long as they stay below what the load would handle.

I would have to go back to Buildzoid's 1080 TI FE PCB analysis, but I believe that board used three feeds from the PCIe 8 and 6 pin connectors. Given the six available power pins, this would have been two pins per section of the core regulator. I seem to recall three shunts as well for measuring the input current.

Watch the video, I'm sure it will clarify things: GTX 1080 Ti Founders Edition PCB Analysis & Shunt Mods

So it looks like the 1080 TI FE current balances the pins in pairs. Each pair is kept to within limits.

Also watch the video Buildzoid did on the EVGA 1080 TI FTW: EVGA Goes Insane with 1080 Ti FTW3 PCB (VRM Analysis)

If you really feeling frisky, watch Buildzoid's video on the 5090 - if you understand the 1080 TI videos, you'll understand why he tore apart the 5090: How Nvidia made the 12VHPWR connector even worse.
 
I think somethings the wording here balls things up, as the term load balancing implies "equal", but it really does not. The don't have to be equal as long as they stay below what the load would handle.

I would have to go back to Buildzoid's 1080 TI FE PCB analysis, but I believe that board used three feeds from the PCIe 8 and 6 pin connectors. Given the six available power pins, this would have been two pins per section of the core regulator. I seem to recall three shunts as well for measuring the input current.

Watch the video, I'm sure it will clarify things: GTX 1080 Ti Founders Edition PCB Analysis & Shunt Mods

So it looks like the 1080 TI FE current balances the pins in pairs. Each pair is kept to within limits.

Also watch the video Buildzoid did on the EVGA 1080 TI FTW: EVGA Goes Insane with 1080 Ti FTW3 PCB (VRM Analysis)

If you really feeling frisky, watch Buildzoid's video on the 5090 - if you understand the 1080 TI videos, you'll understand why he tore apart the 5090: How Nvidia made the 12VHPWR connector even worse.
Yeah, I believe current max limiting might be better than no load balancing. But mainly because it more closely approximates the actual correct form of load balancing, equalizing power loss across all of the pins (volt drop * current). However with any of these balancing methods I still wouldn't be comfortable with this connector. Either add a better connector or require 2x 12vhpwr connectors on the 5090, i dont care. At that point you can do, no load balancing, current max limiting, or power loss balancing, i dont care.

I briefly looked through those videos, but im not sure what you wanted me to get out of them. I dont think he goes into any of the details that we got into.
 
Yeah, I believe current max limiting might be better than no load balancing. But mainly because it more closely approximates the actual correct form of load balancing, equalizing power loss across all of the pins (volt drop * current). However with any of these balancing methods I still wouldn't be comfortable with this connector. Either add a better connector or require 2x 12vhpwr connectors on the 5090, i dont care. At that point you can do, no load balancing, current max limiting, or power loss balancing, i dont care.
The irony here is the connector itself may be okay with proper current management. ETA: The fact that most of the existing 12VHPWR connectors are not burning up lends credence to this.

It may be worth it for you to do a thought experiment: What is a better connector? What would a better connector look like? Why is it better?

While you are doing that, see below, and change your thought experiment to: What would a better power input solution look like?

I briefly looked through those videos, but im not sure what you wanted me to get out of them. I dont think he goes into any of the details that we got into.
Grab yourself a favorite beverage and take the time to watch at least one of them. What he talks about in there is the basis of this entire discussion. I cued up the 1080 TI FE one to the section on shunts where he talks about "how do we blow this up?" - that is a key part of why the card/connector don't blow up if you leave the shunts alone. Then watch it from the beginning.

Then watch the 1080 TI FTW video to see how EVGA altered the card to use more power while staying with the PCIe power specs.

Then watch the 5090 one and see how Nvidia screwed the pooch here.

Repeat after me:

It's not just the connector.
It's not just the connector.
It's not just the connector.

:cool:
 
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NVIDIA RTX 5090 Gets Quad 8-Pin Power Connector Mod To Bypass Melting-Prone 12V-2×6, Nearly Halves Current Per Wire​

Sebastian Castellanos Oct 16, 2026 at 07:31am EDT

A Modder Has Developed A Quad 8-Pin PCIe Power Connector Conversion For NVIDIA's RTX 5090, Promising Significantly Lower Currents And Temperatures Than The Standard 16-Pin Connector​


https://wccftech.com/nvidia-rtx-509...prone-12v-2x6-nearly-halves-current-per-wire/
From the link:

"Interestingly, the conversion has already been tested at up to 800W using a shunt-modded RTX 5090, although such testing doesn't establish long-term reliability or safety at power levels exceeding standard specifications. The module incorporates fused power connections, with optional active monitoring and current-limiting functionality also planned. More detailed testing, including live current and temperature measurements and a 24-hour sustained load, is reportedly underway."

The PCIe 8 connectors would replace the 12VHPWR connector, but would still be saddled by the single 5090 power feed. That could still be enough to burn up the PCIe 8 pin connectors. From the above it sounds like they are planning to address that on this adapter as well with the current limiting.
 
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The above may be an interesting data point due to:

1) 5080 FE
2) The board was power limited to 300W via 84% power limit

This makes the "600W" label on that connector embarrassing -- it failed at 50% load!

And yes, if they are failing at 300W, it makes perfect sense to conclude they will fail more at 500W and 600W. Don't need no stinking statistics to say that.
mine failed at 613+ watts
 
The irony here is the connector itself may be okay with proper current management. ETA: The fact that most of the existing 12VHPWR connectors are not burning up lends credence to this
What do you mean, most 12vhpwr connectors are not burning up? You mean failure rates on 3090 are lower? Do we have the failure rates?
 
What do you mean, most 12vhpwr connectors are not burning up? You mean failure rates on 3090 are lower? Do we have the failure rates?
I mean most of the 12VHPWR connector samples out in the wild today are not failing -- it indicates they are marginal. Some, a small number, are failing.

If most were failing I'm sure it would be holy hell.

Another cringe worthy thing about this whole fiasco is checking a 12VHPWR connector for burning by disconnecting and looking at it contributes to the problem because connectors are only rated for so many mating cycles.
 
I mean most of the 12VHPWR connector samples out in the wild today are not failing -- it indicates they are marginal. Some, a small number, are failing.

If most were failing I'm sure it would be holy hell.

Another cringe worthy thing about this whole fiasco is checking a 12VHPWR connector for burning by disconnecting and looking at it contributes to the problem because connectors are only rated for so many mating cycles.
So you think physically checking the connector 30 to 50 times is the root cause?
 
So you think physically checking the connector 30 to 50 times is the root cause?
I don't think additional disconnects and connects are good for the connector. Ideally connect it once and leave it alone. However...

It's like checking if the light actually turns off in the refrigerator if you close the door, you have to pull the connector to check it.

It may be an argument for using one of those monitors/protecting devices. Connect it, leave it alone until it tells you there is a problem.
 
I mean most of the 12VHPWR connector samples out in the wild today are not failing -- it indicates they are marginal. Some, a small number, are failing.

If most were failing I'm sure it would be holy hell.
And how does that lead credence to the idea that current management will fix it?
 
And how does that lead credence to the idea that current management will fix it?
I'm kind of running out of approaches to explain it to you. Review the previous material and watch this: How Nvidia made the 12VHPWR connector even worse.

Those shunts he is talking about -- that's how the current balancing is implemented on some cards (3090TI) and not others (5090 FE). The same shunting used on the 3090TI was done on the 1080 TI FE and Titan Xp. I believe the shunting on the 1080 TI FTW3 was even better (4 shunts), but I'm not sure. Each shunt is used to supply a specific input to the core power regulator. They are not shared, one core regulator input cannot steal from another source that is not connected to its shunt. This forces the splitting of the supply current across multiple conductors on the connector and eases the sensitivity to the variation in contact resistance in the connector.

The only other advice I can give is stop thinking of the connector as "bad" and look at the whole thing from the 12V source to the input(s) of the core regulators on the PCB. You cannot understand this problem without understanding that part of the PCB. The whole solution is problematic, but the connector may just be a victim of the PCB design.
 
I'm kind of running out of approaches to explain it to you. Review the previous material and watch this: How Nvidia made the 12VHPWR connector even worse.

Those shunts he is talking about -- that's how the current balancing is implemented on some cards (3090TI) and not others (5090 FE). The same shunting used on the 3090TI was done on the 1080 TI FE and Titan Xp. I believe the shunting on the 1080 TI FTW3 was even better (4 shunts), but I'm not sure. Each shunt is used to supply a specific input to the core power regulator. They are not shared, one core regulator input cannot steal from another source that is not connected to its shunt. This forces the splitting of the supply current across multiple conductors on the connector and eases the sensitivity to the variation in contact resistance in the connector.

The only other advice I can give is stop thinking of the connector as "bad" and look at the whole thing from the 12V source to the input(s) of the core regulators on the PCB. You cannot understand this problem without understanding that part of the PCB. The whole solution is problematic, but the connector may just be a victim of the PCB design.
No, he's right, you're just arguing in circles. Current management allows you to catch a failure. It doesn't prevent the failure itself. In terms of total heat generated in the connector, connecting everything in parallel generates the lowest overall heat, but that's not what we're aiming for. We're trying to avoid a situation where the gradual shift of current among the pins goes undetected until the connector burns up. Current monitoring like the Wireview Pro also accomplishes the same thing but with much more expensive hardware since measuring current is inherently harder than measuring voltage. Connector temperature measurement has proven to be inadequate protection.
 
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