HardOCP News
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I'll bet this is just Samsung getting back at Apple for all the lawsuits.
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Thing is...smaller the nodes go, the hotter chips can get so heat dissipation/thermal management must also be adapted to the smaller node size.
Thing is...smaller the nodes go, the hotter chips can get so heat dissipation/thermal management must also be adapted to the smaller node size.
Actually, it's the other way around. Die shrinkage means less heat for the same design.
16nm?
14nm?
PR FUD
It's shame only Intel is sticking to their normal naming convention...and everybody else is renaming their process...even if gate and picth dosn't alter...sad, sad state of affairs
@techrat... yes die shrinkage means less heat for the same design, however MoFoQ said "hot" which is different than heat.
While you are right that smaller nanometer processes on the same design produces less heat, it also means you have a design doing the same amount of work in a much denser area. This can lead to a chip running "hotter" in terms of temperature, but produces less overall heat. (Like we have seen with haswell vs. sandybridge for example)
16nm?
14nm?
PR FUD
http://www.extremetech.com/wp-content/uploads/2014/12/Cell-SizeComparison.png[/I MG]
It's shame only Intel is sticking to their normal naming convention...and everybody else is renaming their process...even if gate and picth dosn't alter...sad, sad state of affairs :([/QUOTE]Both TSMC and Samsung had explained their hybrid node process a couple of years ago. That is what was expected.
Even I was snarking on it 2 years ago based on its characteristics: [url]http://hardforum.com/showpost.php?p=1040313878&postcount=38[/url]
[quote="pxc, post: 1040313878"]... The Alliance's upcoming 14/16nm node... is a hybrid node with performance characteristics and density not improved much from the 20nm node.[/QUOTE]
As a general rule when you implement the same design on a smaller node you produce less heat. Working on a smaller node allows you to make design decisions that lead to a hotter chip, but the node itself doesn't inherently do that.
The two chips won't be otherwise identical because the two processes almost certainly have different design rules, but if anything I'd bet on the samsung chips being cooler.
Yet it's the smaller Samsungs that are running hotter and using up more battery life.
There's speculation that the TSMCs might be throttling and doing less work than the Samsung, but I have yet to see anyone talk about running a test that shows which version of the phone has faster performance, unless I have missed something obvious.
My first 6S had Samsung chip, and it was noticeably hotter and uncomfortable to use.
16nm?
14nm?
PR FUD
It's shame only Intel is sticking to their normal naming convention...and everybody else is renaming their process...even if gate and picth dosn't alter...sad, sad state of affairs
You're quoting FUD that has been disproved. Look to an expert like Chipworks for facts.
https://www.chipworks.com/about-chipworks/overview/blog/a9-is-tsmc-16nm-finfet-and-samsung-fabbed
http://www.chipworks.com/sites/default/files/blog%20image6.jpg[/I MG][/QUOTE]You're comparing real apples and banana shaped rocks. The other image shows the dimensions of M1 and gate pitch as described by each manufacturer. As I quoted myself above, the 14nm and 16nm modes from Alliance members are hybrids and didn't get full geometry benefits expected in a node shrink.
Showing that chipworks die size comparison actually supports the other image. lol
The problem is differences in battery life.People always find something to flip over about. We have a 6s (sammy) and a 6s plus (tsmc) in use and I have yet to notice any real difference between the two even if they really cant be directly compared due to obvious differences. Even that geekbench app shows them pretty much identical in terms of performance no matter how many times i run it
article said:Speaking to TechCrunch, Apple has pointed out that real-world usage is far more reflective of how an iPhone is used that the benchmarking tests, and that in normal use the variance between the two handsets is on the order or two or three percent. Given tolerances in manufacturing, this performance is within the margin of error that many would expect in consumer electronics.
You're comparing real apples and banana shaped rocks. The other image shows the dimensions of M1 and gate pitch as described by each manufacturer. As I quoted myself above, the 14nm and 16nm modes from Alliance members are hybrids and didn't get full geometry benefits expected in a node shrink.
Showing that chipworks die size comparison actually supports the other image. lol
A great deal of discussion ensued over whether Samsung’s 14nm process really represented a “true” die shrink over its 20nm predecessor. We were ourselves surprised to see Chipworks announce that the piece came in at only 78mm² compared to the Exynos 5433’s 113mm². This 31% shrink was beyond what we expected, as we previously reported that Samsung’s 14nm process was to continue to use the 20nm’s BEOL (Back-End-Of-Line, a chip’s largest metal layer) and thus make for only a minor progression.
The problem is differences in battery life.
Apple Confirms 'Good And Bad' iPhone 6S Chips Offer You Shorter Battery Life
A common use where this power drain difference would show outside of benchmarking is in mobile gaming, especially if it's more than minimally taxing.
Probably right but 2 extra hours seems insane. But you'd need two identical phones to compare, I cant test or judge that on these
2 hours delta is very fishy. I know there are a lot of variables due to second sourcing components, batteries, etc. that may make a small single digit % difference but 2 hours I blame on nationalistic Chinese media supporting Chinese TSMC fab.
Samsung produces worse products than some "garbage Chinese manufacturer"? Impossibru!!!!
What part don't you understand that the true die size as shown by Chipworks shows a narrower and shorter die size invalidating the first picture which purports to show the same vertical dimension for TSMC 20nm/16nm and Samsung 14nm?
You don't understand the picture or what I wrote AT ALL. lolWhat part don't you understand that the true die size as shown by Chipworks shows a narrower and shorter die size invalidating the first picture which purports to show the same vertical dimension for TSMC 20nm/16nm and Samsung 14nm?
lolWhat do you think the C in Taiwan ROC/PRC stands for?
Each chip is going to have a totally different physical design, so it's not a particularly effective way to compare process area/density. Same goes for power consumption.
You don't understand the picture or what I wrote AT ALL. lol
Seriously, lol.
You're quoting FUD that has been disproved. Look to an expert like Chipworks for facts.
https://www.chipworks.com/about-chipworks/overview/blog/a9-is-tsmc-16nm-finfet-and-samsung-fabbed
Both TSMC and Samsung had explained their hybrid node process a couple of years ago. That is what was expected.
Even I was snarking on it 2 years ago based on its characteristics: http://hardforum.com/showpost.php?p=1040313878&postcount=38
That's about as ignorant as saying Texas is not USA. What do you think the C in Taiwan ROC/PRC stands for?
That's about as ignorant as saying Texas is not USA. What do you think the C in Taiwan ROC/PRC stands for?