Intel's Haswell Architecture

[aphexcoil]

Let's talk about Intel's upcoming Haswell architecture for a moment. What information is there about this new architecture?

As we know, Haswell will be a "tick" in Intel's "tick-tock" engineering and development schedule. Ivy Bridge, which is due out in the first half of next year, is a reduction in size of the current Sandy Bridge architecture. However, Intel refers to this next release as a "tock +" release due to some small architectural enhancements (support for DirectX v11, etc.).

The Haswell chip will be produced using 22nm lithography. Intel has hinted at support for "multiple OS's" with Haswell, however I am a bit unclear as to what they mean by this.

What other major enhancements will Haswell bring to the table, though? I've heard talk of a new instruction set being introduced. I'd also assume that Intel will release a more balanced GPU along with the CPU.

What does everyone know thus far about this chip?

Thanks!

 

[Cyberbeing]

It is really to early to be talking about Haswell considering it's likely destined for 2013, and we don't even have SandyBridge-E or IvyBridge yet.

The AVX2 instruction set (i.e. AVX for integers) looks to be the most exciting thing so far, with its potential to double integer performance on optimized applications. That could lead to a massive speed boost doing x264 encoding for example, not to mention availability of 8-core mainstream processors.

The "multiple OS's" thing probably means that plan to make Haswell chips for mobile phones, tablets, and low-power netbooks running alternative OS like Android.

 

[Catalina588]

Haswell is still hazy, but there's plenty of information out there. Intel has started talking in general terms about capabilities (see here and about the micro-architecture at Wikipedia). An older story at The Reg talks about a native octo-core design. (Sounds like Bulldozer, perhaps).

 

[c0d1f1ed]

As we know, Haswell will be a "tick" in Intel's "tick-tock" engineering and development schedule.

No, Haswell be a "tock", which means it will have significant architectural changes.

Ivy Bridge, which is due out in the first half of next year, is a reduction in size of the current Sandy Bridge architecture. However, Intel refers to this next release as a "tock +" release due to some small architectural enhancements (support for DirectX v11, etc.).

Ivy Bridge is a "tick+". The plus most likely refers to Tri-Gate technology. Others will move to 22 nm technology without such technology, so Intel will have a significant advantage over just the process shrink alone.

What other major enhancements will Haswell bring to the table, though? I've heard talk of a new instruction set being introduced.

The AVX2 instruction set could revolutionize high-throughput computing. It features support for "gather" instructions, which access multiple independent memory locations. One gather instruction replaces up to 18 legacy instructions!

Other than that it also features fused multiply-add support, which could double the theoretical floating-point performance. And finally it also extends integer vector operations to 256-bit. All this also suggests they'll have to increase the bandwidth.

So Haswell is looking like it could be a major leap forward, offering GPU-like throughput performance while retaining the flexibility of a CPU.

 

[c0d1f1ed]

The AVX2 instruction set (i.e. AVX for integers) looks to be the most exciting thing so far, with its potential to double integer performance on optimized applications. That could lead to a massive speed boost doing x264 encoding for example...

Without a doubt the most revolutionary thing about AVX2 is the gather instruction support. They borrowed that from the Larrabee project. Even though Larrabee itself has not yet been able to measure up to GPUs (especially at legacy graphics), adding gather support to the CPU makes a lot of sense.

It's the vector equivalent of a load instruction, with independent addesses per element. This allows to efficiently vectorize code loops, even when there are table lookups or when there's so-called pointer chasing. Previously developers had to alter their algorithms to avoid these things, which resulted in a performance loss.

Some loops which were previously not vectorizable, might run up to eight times faster with AVX2!

 

[sethk]

No, Haswell be a "tock", which means it will have significant architectural changes.

Ivy Bridge is a "tick+". The plus most likely refers to Tri-Gate technology. Others will move to 22 nm technology without such technology, so Intel will have a significant advantage over just the process shrink alone.

The AVX2 instruction set could revolutionize high-throughput computing. It features support for "gather" instructions, which access multiple independent memory locations. One gather instruction replaces up to 18 legacy instructions!

Other than that it also features fused multiply-add support, which could double the theoretical floating-point performance. And finally it also extends integer vector operations to 256-bit. All this also suggests they'll have to increase the bandwidth.

So Haswell is looking like it could be a major leap forward, offering GPU-like throughput performance while retaining the flexibility of a CPU.

That's just.. MADD!

 

[vkaraoke]

That's just.. MADD!

Mother's Against Drunk Driving?

 

[doz]

And here we are again, talking about things that are atleast a year off if not longer.....

When are we going to give it a rest? I still want socket 2011 and you are talking about something 6-12 months beyond that.

Hmmm, can we talk about the integrated graphics Intel will be using in 2015? Think itll be comparable to a 6970?

 

[pxc]

OP: the main things Intel has mentioned for the Haswell architecture are a change in cache architecture and FMA3 support included in AVX2. Little more information has been official.

FMA3/4 was originally supposed to be included in SNB, but it was removed from the specs. It probably exists in SNB CPUs, but the instructions are not enabled.

And here we are again, talking about things that are atleast a year off if not longer.....

Isn't it easier to hit the back button than to complain? Very little information about Haswell has been released by Intel and it's easy to answer the OP's valid question.

 

[pxc]

And one other bit of information: http://www.sweclockers.com/nyhet/14288-intel-ger-stod-for-directx-111-i-haswell

Haswell is getting a newer GPU (Denlow) capable of DX 11.1, which is the version that may be coming with Windows 8 as speculated in the link.

 

[xBanzai89]

No DX12? Well maybe thats good so developers actually adapt to one before even getting started taking advantage of it.

 

[c0d1f1ed]

FMA3/4 was originally supposed to be included in SNB, but it was removed from the specs. It probably exists in SNB CPUs, but the instructions are not enabled.

I doubt that. FMA support was a separate CPUID flag in the March 2008 AVX Programming Reference. So it doesn't seem they ever intended to introduce AVX and FMA in the same architecture.

And apart from that, FMA also demands higher cache bandwidth. But they already included a second 128-bit load unit in Sandy Bridge to support 256-bit load operations. My expectation is that Haswell will have two 256-bit load units and one 256-bit store unit (with possibly only the second load unit capable of gather operations, at a slightly higher latency). These changes are very substantial, so I don't think they were ever planned for Sandy Bridge nor its shrink Ivy Bridge.

 

[sirmonkey1985]

No DX12? Well maybe thats good so developers actually adapt to one before even getting started taking advantage of it.

11 and 11.1 shouldn't be any different.. its the equivalent of DX9 and DX9A B and C basically.. just a sales gimmick for microsoft. wouldn't surprise me if they change the naming scheme for directx when they replace the windows brand as well.

 

[pxc]

I doubt that.

You can, but Intel itself is the one who pulled FMA well into the design of SNB. That's why it's likely in SNB, but not enabled.

Flags are not what limit support exclusively. The VEX instruction encoding for AVX/AVX2 is what allow SNB/IB to support various new SIMD instructions of multiple operands. AMD used that very encoding with BD for its FMA instructions.

 

[c0d1f1ed]

You can, but Intel itself is the one who pulled FMA well into the design of SNB. That's why it's likely in SNB, but not enabled.

Could you point me to an official statement where Sandy Bridge was claimed to have FMA support? Here's an October 2008 post from an Intel engineer confirming Sandy Bridge not to have FMA support: http://software.intel.com/en-us/forums/showthread.php?t=61121.

Flags are not what limit support exclusively. The VEX instruction encoding for AVX/AVX2 is what allow SNB/IB to support various new SIMD instructions of multiple operands. AMD used that very encoding with BD for its FMA instructions.

AMD had planned FMA support for its SSE5 extension from the beginning. It's only after Intel announced AVX that they dropped SSE5 and adopted VEX encoding. They simply had to pair up the 128-bit ALUs in the FlexFP unit, and obviously they kept the FMA support.

Basically AMD added FMA without really widening the ALUs, while Intel first widened the ALUs and will add FMA with Haswell. Obviously AMD will have to widen the ALUs to keep up with Intel.