p4 quad fsb, what does it do

[-ChEM-]

is there any point to the 4xfsb thing on p4s (and 2x on amds) except better syncing with ram.. if not, why? does it just send the same information 4 times or something?

or is it bottlenecked by the fsb? if thats the case then why is ddr ram better than sdr?

 

[pxc]

Increasing the bus speed with frequency or data rate increases the memory/data bandwidth available to the processor. The P4s use it to increase the memory bandwidth to the processor: 200MHz QDR = 800MHz effective for 64-bit transfers gives 6.4GB/s of memory/bus bandwidth.

AMD uses a 16-bit 800MHz HyperTransport (DDR... 1600MHz effective) link to the remnants of north bridge functionality (AGP + link to "south bridge"). The memory controller is built into the CPU and it doesn't really have a classical FSB speed anymore since the HT link and memory controllers are on chip. The single channel S754 chips have 3.2GB/s of memory bandwidth and dual channel S939/940 chips have 6.4GB/s of memory bandwidth. Plus both have 3.2GB/s of HT bandwidth. The total bandwidth equals or exceeds the 800MHz FSB P4 CPUs FSB bandwidth.

In case you're interested, this is how single, double, quad and oct (AGP8x, for example) work in one clock cycle:

|------| 1 clock cycle
 ___
|   |___| 1 data transfer per clock (single data rate)
x-------
 ___
|   |___| 2 data transfers per clock (double data rate DDR)
x---x---
 ___
|   |___| 4 data transfers per clock (quad data rate QDR)
x-x-x-x-
 ___
|   |___| 8 data transfers per clock (oct data rate ODR)
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