![[H]ard|Forum](/styles/hardforum/xenforo/logo_dark.png){kind=logo}
- Joined
- Dec 19, 2005
- Messages
- 18,295
A new technology called PowerVia or PowerVIA
"A Unique Test Chip with Intentional, Hidden Bugs
The last part of that conclusion—"acceptable debug times"—is a critical achievement alongside the product improvements. Today, chip-testing techniques are based on the accessibility of the transistors in that first and lowest layer. With the transistors now sandwiched in the middle of the chip, "a lot of those techniques had to be redeveloped," says Sell.
"There were a lot of concerns and hesitancy and that was probably the hardest thing to figure out—how to do debug on this new backside power delivery." To make things even more challenging, the test chip design team intentionally added some "Easter egg" errors to the chip, unbeknownst to the validation team. The good news? They found the bugs.
"We have made tremendous progress over the last couple of years in developing those debug capabilities and proving them on Blue Sky Creek," Sell asserts.
That brings up one more novel thing about how Sell and the Intel team figured out the PowerVia recipe. PowerVia will be introduced into Intel-manufactured silicon starting with the Intel 20A node, which enters production in 2024 (Intel 20A will also see the introduction of a new gate-all-around transistor design called RibbonFET; customers of Intel Foundry Services can benefit from both innovations in the subsequent Intel 18A node, arriving later in 2024). To isolate the development of PowerVia, they took the well-proven transistors from the preceding Intel 4 process node and built a special in-between node with the power and interconnect design planned for Intel 20A.
A Special Test Process Node to Isolate Backside Power
And while Intel manufacturing and design teams regularly create all manner of Frankenstein test-chips—to test new designs and intellectual properties and to solidify silicon processes—they don't usually make them as functional and complete as Blue Sky Creek. In this case, the teams needed to verify not only that they could build and test a chip this way, but also that the new configuration wouldn't bring new issues into the final product.
For instance, heat. "Normally you use the silicon side also for heat dissipation," Sell explains. "So now you have sandwiched your transistors and the question is, 'Do we have a thermal problem? Do we get a lot of local heating?'" At this point you can probably guess the answer: no.
"What was most amazing," Sell recalls, "was despite these radical changes"—sandwiching transistors in the middle of the chip and introducing this heavy "polishing" to the process—"we could make the transistors look very, very close to what we had in Intel 4."
As for PowerVia, it has no peer. According to recent reports, Intel's planned 2024 introduction of PowerVia would put competitors "roughly two years behind" when it comes to backside power.
"At least for this time period," confirms Sell, "we have a quite competitive backside power delivery option."
Your first opportunity to feel the many benefits of PowerVia will come next year in the form of Arrow Lake, a next-generation Intel processor for PCs built using the Intel 20A process. Its billions of transistors will be inverted, working more efficiently than ever."
Source: https://www.techpowerup.com/309636/with-powervia-intel-achieves-a-chipmaking-breakthrough
"A Unique Test Chip with Intentional, Hidden Bugs
The last part of that conclusion—"acceptable debug times"—is a critical achievement alongside the product improvements. Today, chip-testing techniques are based on the accessibility of the transistors in that first and lowest layer. With the transistors now sandwiched in the middle of the chip, "a lot of those techniques had to be redeveloped," says Sell.
"There were a lot of concerns and hesitancy and that was probably the hardest thing to figure out—how to do debug on this new backside power delivery." To make things even more challenging, the test chip design team intentionally added some "Easter egg" errors to the chip, unbeknownst to the validation team. The good news? They found the bugs.
"We have made tremendous progress over the last couple of years in developing those debug capabilities and proving them on Blue Sky Creek," Sell asserts.
That brings up one more novel thing about how Sell and the Intel team figured out the PowerVia recipe. PowerVia will be introduced into Intel-manufactured silicon starting with the Intel 20A node, which enters production in 2024 (Intel 20A will also see the introduction of a new gate-all-around transistor design called RibbonFET; customers of Intel Foundry Services can benefit from both innovations in the subsequent Intel 18A node, arriving later in 2024). To isolate the development of PowerVia, they took the well-proven transistors from the preceding Intel 4 process node and built a special in-between node with the power and interconnect design planned for Intel 20A.
A Special Test Process Node to Isolate Backside Power
And while Intel manufacturing and design teams regularly create all manner of Frankenstein test-chips—to test new designs and intellectual properties and to solidify silicon processes—they don't usually make them as functional and complete as Blue Sky Creek. In this case, the teams needed to verify not only that they could build and test a chip this way, but also that the new configuration wouldn't bring new issues into the final product.
For instance, heat. "Normally you use the silicon side also for heat dissipation," Sell explains. "So now you have sandwiched your transistors and the question is, 'Do we have a thermal problem? Do we get a lot of local heating?'" At this point you can probably guess the answer: no.
"What was most amazing," Sell recalls, "was despite these radical changes"—sandwiching transistors in the middle of the chip and introducing this heavy "polishing" to the process—"we could make the transistors look very, very close to what we had in Intel 4."
As for PowerVia, it has no peer. According to recent reports, Intel's planned 2024 introduction of PowerVia would put competitors "roughly two years behind" when it comes to backside power.
"At least for this time period," confirms Sell, "we have a quite competitive backside power delivery option."
Your first opportunity to feel the many benefits of PowerVia will come next year in the form of Arrow Lake, a next-generation Intel processor for PCs built using the Intel 20A process. Its billions of transistors will be inverted, working more efficiently than ever."
Source: https://www.techpowerup.com/309636/with-powervia-intel-achieves-a-chipmaking-breakthrough
