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- Joined
- Dec 19, 2005
- Messages
- 18,789
I love those hardcore Enterprise hardwares.
"“It turns out that by now, their 14 nm node is pretty good and there are decent overhead margins on the bitlines and wordlines. Tinkering with their z14 cells, they were able to double the bitline and wordline lengths within those margins.”
This allowed the number of sub-arrays to be halved to eight, using blocks of 2MiB instead of 1MiB previously. This reduced the I/O overhead and increased density by 30%. Power delivery changes accounted for another 38%, according to WikiChip, making for a total improvement in effective cache density of 80% higher MiB/mm2.
The L1 and L2 caches consist of SRAM cells and run at 5.2GHz, the L3 and L4 eDRAM caches run at 2.6GHz."
https://www.tomshardware.com/uk/news/ibm-z15-almost-doubles-cache-density-features-960mib-l4-edram
"“It turns out that by now, their 14 nm node is pretty good and there are decent overhead margins on the bitlines and wordlines. Tinkering with their z14 cells, they were able to double the bitline and wordline lengths within those margins.”
This allowed the number of sub-arrays to be halved to eight, using blocks of 2MiB instead of 1MiB previously. This reduced the I/O overhead and increased density by 30%. Power delivery changes accounted for another 38%, according to WikiChip, making for a total improvement in effective cache density of 80% higher MiB/mm2.
The L1 and L2 caches consist of SRAM cells and run at 5.2GHz, the L3 and L4 eDRAM caches run at 2.6GHz."
https://www.tomshardware.com/uk/news/ibm-z15-almost-doubles-cache-density-features-960mib-l4-edram