Haswell's on-die VRM

[pxc]

http://www.xbitlabs.com/news/cpu/di...rete_Weapon_Integrated_Voltage_Regulator.html

The first Intel slide is interesting for the other spaces shown in the other corners from the on-package VRM. Could that be spaces for the models which include "stacked" memory?

Haswell supposedly cuts active idle power by a factor of 20x over IB. The smart VRM on-package should be a part of that decrease. Maybe not too interesting on the desktop, but it should help extend mobile battery life under "typical use" where the CPU is often idle.

 

[KazeoHin]

I wonder how the MoBos will work with this new mini VRM. will they have more room for things like mini PCIE slots, or more space for additional dimms of RAM?

 

[pxc]

It should free up some space around the motherboard, but the boards will probably continue having some simpler kind of VRM to feed the processor's on-package VRM. I'd guess the change will just allow the PCB to be a bit smaller in the front to back dimension, also due to Haswell being a SoC device.

Looking through the IDF 2012 slide deck, it's pretty clear that Intel reached "Fusion" (SoC with CPU and GPU intertwined tightly, and not only through a shared LLC) with Haswell before AMD could fully integrate the GPU + CPU in its own processors. Too bad Intel doesn't offer a "to the metal" API which would allow even fuller integration (lots of problems involved with that, but at least HPC could benefit more). Full Fusion is still a couple of years out for AMD in its next architecture.

Some of the other tidbits were interesting too, like Intel mentioning that an 8W Haswell processor could integrated a full GT3 GPU, which kind of previews what Intel has in mind for the cut down version in the next gen Atoms next year, and that L1/L2 cache bandwidth was doubled at the same latencies over Ivy Bridge's already very fast caches (L3 cache in Haswell is slower than IB, but overall shouldn't cause a performance decrease due to the inclusive L1/L2).